关键词：rk3126.dtsi ,linux_3.10,rockchip,dts
dts — rk3126.dtsi
#include "rk312x.dtsi" / { compatible = "rockchip,rk3126"; }; &cru { compatible = "rockchip,rk3126-cru"; }; -frequency = <0>; #clock-cells = <0>; }; clk_tsp_in: clk_tsp_in { compatible = "rockchip,rk-fixed-clock"; clock-output-names = "clk_tsp_in"; clock-frequency = <0>; #clock-cells = <0>; }; dummy: dummy { compatible = "rockchip,rk-fixed-clock"; clock-output-names = "dummy"; clock-frequency = <0>; #clock-cells = <0>; }; dummy_cpll: dummy_cpll { compatible = "rockchip,rk-fixed-clock"; clock-output-names = "dummy_cpll"; clock-frequency = <0>; #clock-cells = <0>; }; }; fixed_factor_cons { compatible = "rockchip,rk-fixed-factor-cons"; clk_gpll_div2: clk_gpll_div2 { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_gpll>; clock-output-names = "clk_gpll_div2"; clock-div = <2>; clock-mult = <1>; #clock-cells = <0>; }; clk_gpll_div3: clk_gpll_div3 { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_gpll>; clock-output-names = "clk_gpll_div3"; clock-div = <3>; clock-mult = <1>; #clock-cells = <0>; }; g_clk_pvtm_func: g_clk_pvtm_func { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&xin24m>; clock-output-names = "g_clk_pvtm_func"; clock-div = <1>; clock-mult = <1>; #clock-cells = <0>; }; hclk_vepu: hclk_vepu { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_vepu>; clock-output-names = "hclk_vepu"; clock-div = <4>; clock-mult = <1>; #clock-cells = <0>; }; hclk_vdpu: hclk_vdpu { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_vdpu>; clock-output-names = "hclk_vdpu"; clock-div = <4>; clock-mult = <1>; #clock-cells = <0>; }; pclkin_cif_inv: pclkin_cif_inv { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_gates3 3>; clock-output-names = "pclkin_cif_inv"; clock-div = <1>; clock-mult = <1>; #clock-cells = <0>; }; hclk_vio_niu: hclk_vio_niu { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&hclk_vio_pre>; clock-output-names = "hclk_vio_niu"; clock-div = <1>; clock-mult = <1>; #clock-cells = <0>; }; aclk_vio0_niu: aclk_vio0_niu { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&aclk_vio0_pre>; clock-output-names = "aclk_vio0_niu"; clock-div = <1>; clock-mult = <1>; #clock-cells = <0>; }; aclk_vio1_niu: aclk_vio1_niu { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&aclk_vio1_pre>; clock-output-names = "aclk_vio1_niu"; clock-div = <1>; clock-mult = <1>; #clock-cells = <0>; }; }; pd_cons { compatible = "rockchip,rk-pd-cons"; pd_gpu: pd_gpu { compatible = "rockchip,rk-pd-clock"; clock-output-names = "pd_gpu"; rockchip,pd-id = <CLK_PD_GPU>; #clock-cells = <0>; }; pd_video: pd_video { compatible = "rockchip,rk-pd-clock"; clock-output-names = "pd_video"; rockchip,pd-id = <CLK_PD_VIDEO>; #clock-cells = <0>; }; pd_vio: pd_vio { compatible = "rockchip,rk-pd-clock"; clock-output-names = "pd_vio"; rockchip,pd-id = <CLK_PD_VIO>; #clock-cells = <0>; }; pd_vop: pd_vop { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_vop"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_vip: pd_vip { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_vip"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_iep: pd_iep { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_iep"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_rga: pd_rga { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_rga"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_ebc: pd_ebc { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_ebc"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_mipidsi: pd_mipidsi { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_mipidsi"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; pd_hdmi: pd_hdmi { compatible = "rockchip,rk-pd-clock"; clocks = <&pd_vio>; clock-output-names = "pd_hdmi"; rockchip,pd-id = <CLK_PD_VIRT>; #clock-cells = <0>; }; }; clock_regs { compatible = "rockchip,rk-clock-regs"; #address-cells = <1>; #size-cells = <1>; reg = <0x0000 0x01f0>; ranges; /* PLL control regs */ pll_cons { compatible = "rockchip,rk-pll-cons"; #address-cells = <1>; #size-cells = <1>; ranges ; clk_apll: pll-clk@0000 { compatible = "rockchip,rk3188-pll-clk"; reg = <0x0000 0x10>; mode-reg = <0x0040 0>; status-reg = <0x0004 10>; clocks = <&xin24m>; clock-output-names = "clk_apll"; rockchip,pll-type = <CLK_PLL_3036_APLL>; #clock-cells = <0>; }; clk_dpll: pll-clk@0010 { compatible = "rockchip,rk3188-pll-clk"; reg = <0x0010 0x10>; mode-reg = <0x0040 4>; status-reg = <0x0014 10>; clocks = <&xin24m>; clock-output-names = "clk_dpll"; rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>; #clock-cells = <0>; }; clk_cpll: pll-clk@0020 { compatible = "rockchip,rk3188-pll-clk"; reg = <0x0020 0x10>; mode-reg = <0x0040 8>; status-reg = <0x0024 10>; clocks = <&xin24m>; clock-output-names = "clk_cpll"; rockchip,pll-type = <CLK_PLL_312XPLUS>; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_gpll: pll-clk@0030 { compatible = "rockchip,rk3188-pll-clk"; reg = <0x0030 0x10>; mode-reg = <0x0040 12>; status-reg = <0x0034 10>; clocks = <&xin24m>; clock-output-names = "clk_gpll"; rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>; #clock-cells = <0>; #clock-init-cells = <1>; }; }; /* Select control regs */ clk_sel_cons { compatible = "rockchip,rk-sel-cons"; #address-cells = <1>; #size-cells = <1>; ranges; clk_sel_con0: sel-con@0044 { compatible = "rockchip,rk3188-selcon"; reg = <0x0044 0x4>; #address-cells = <1>; #size-cells = <1>; clk_core_div: clk_core_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_core>; clock-output-names = "clk_core"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE>; rockchip,flags = <(CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)>; }; /* reg[6:5]: reserved */ clk_core: clk_core_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&clk_apll>, <&clk_gpll_div2>; clock-output-names = "clk_core"; #clock-cells = <0>; #clock-init-cells = <1>; }; aclk_cpu_div: aclk_cpu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&aclk_cpu>; clock-output-names = "aclk_cpu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; aclk_cpu: aclk_cpu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <13 2>; clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>; clock-output-names = "aclk_cpu"; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15]: reserved */ }; clk_sel_con1: sel-con@0048 { compatible = "rockchip,rk3188-selcon"; reg = <0x0048 0x4>; #address-cells = <1>; #size-cells = <1>; pclk_dbg_div: pclk_dbg_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 4>; clocks = <&clk_core>; clock-output-names = "pclk_dbg"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; aclk_core_pre: aclk_core_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <4 3>; clocks = <&clk_core>; clock-output-names = "aclk_core_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[7]: reserved */ hclk_cpu_pre: hclk_cpu_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 2>; clocks = <&aclk_cpu>; clock-output-names = "hclk_cpu_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[11:10]: reserved */ pclk_cpu_pre: pclk_cpu_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <12 3>; clocks = <&aclk_cpu>; clock-output-names = "pclk_cpu_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15]: reserved */ }; clk_sel_con2: sel-con@004c { compatible = "rockchip,rk3188-selcon"; reg = <0x004c 0x4>; #address-cells = <1>; #size-cells = <1>; clk_pvtm_div: clk_pvtm_div { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 7>; clocks = <&g_clk_pvtm_func>; clock-output-names = "clk_pvtm"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7]: reserved */ clk_nandc_div: clk_nandc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_nandc>; clock-output-names = "clk_nandc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[13]: reserved */ clk_nandc: clk_nandc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_nandc"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con3: sel-con@0050 { compatible = "rockchip,rk3188-selcon"; reg = <0x0050 0x4>; #address-cells = <1>; #size-cells = <1>; clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_i2s_2ch_pll>; clock-output-names = "clk_i2s_2ch_pll"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; /* reg[7]: reserved */ clk_i2s_2ch: clk_i2s_2ch_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>; clock-output-names = "clk_i2s_2ch"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[11:10]: reserved */ clk_i2s_2ch_out: clk_i2s_2ch_out_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <12 1>; clocks = <&clk_i2s_2ch>, <&xin12m>; clock-output-names = "i2s_clkout"; #clock-cells = <0>; }; /* reg[13]: reserved */ clk_i2s_2ch_pll: i2s_2ch_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_i2s_2ch_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con4: sel-con@0054 { compatible = "rockchip,rk3188-selcon"; reg = <0x0054 0x4>; #address-cells = <1>; #size-cells = <1>; clk_tsp_div: clk_tsp_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_tsp>; clock-output-names = "clk_tsp"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[5]: reserved */ clk_tsp: clk_tsp_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_tsp"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_24m_div: clk_24m_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&xin24m>; clock-output-names = "clk_24m"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[15:13]: reserved */ }; clk_sel_con5: sel-con@0058 { compatible = "rockchip,rk3188-selcon"; reg = <0x0058 0x4>; #address-cells = <1>; #size-cells = <1>; clk_mac_pll_div: clk_mac_pll_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_mac_pll>; clock-output-names = "clk_mac_pll"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; #clock-init-cells = <1>; }; /* reg[5]: reserved */ clk_mac_pll: clk_mac_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_mac_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[14:8]: reserved */ clk_mac_ref: clk_mac_ref_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <15 1>; clocks = <&clk_mac_pll_div>, <&gmac_clkin>; clock-output-names = "clk_mac_ref"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MAC_REF>; rockchip,flags = <CLK_SET_RATE_PARENT>; #clock-init-cells = <1>; }; }; clk_sel_con6: sel-con@005c { compatible = "rockchip,rk3188-selcon"; reg = <0x005c 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_div: spdif_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spdif_pll>; clock-output-names = "clk_spdif_pll"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; /* reg[7]: reserved */ clk_spdif: spdif_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>; clock-output-names = "clk_spdif"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[13:10]: reserved */ clk_spdif_pll: spdif_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_spdif_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con7: sel-con@0060 { compatible = "rockchip,rk3188-selcon"; reg = <0x0060 0x4>; #address-cells = <1>; #size-cells = <1>; i2s_2ch_frac: i2s_2ch_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&clk_i2s_2ch_pll>; clock-output-names = "i2s_2ch_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con8: sel-con@0064 { compatible = "rockchip,rk3188-selcon"; reg = <0x0064 0x4>; #address-cells = <1>; #size-cells = <1>; i2s_8ch_frac: i2s_8ch_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&clk_i2s_8ch_pll>; clock-output-names = "i2s_8ch_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con9: sel-con@0068 { compatible = "rockchip,rk3188-selcon"; reg = <0x0068 0x4>; #address-cells = <1>; #size-cells = <1>; clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_i2s_8ch_pll>; clock-output-names = "clk_i2s_8ch_pll"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; /* reg[7]: reserved */ clk_i2s_8ch: clk_i2s_8ch_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>; clock-output-names = "clk_i2s_8ch"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[13:10]: reserved */ clk_i2s_8ch_pll: i2s_8ch_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "clk_i2s_8ch_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con10: sel-con@006c { compatible = "rockchip,rk3188-selcon"; reg = <0x006c 0x4>; #address-cells = <1>; #size-cells = <1>; aclk_peri_div: aclk_peri_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&aclk_peri>; clock-output-names = "aclk_peri"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; /* reg[7:5]: reserved */ hclk_peri_pre: hclk_peri_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 2>; clocks = <&aclk_peri>; clock-output-names = "hclk_peri_pre"; rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>; rockchip,div-relations = <0x0 1 0x1 2 0x2 4>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[11:10]: reserved */ pclk_peri_pre: pclk_peri_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <12 2>; clocks = <&aclk_peri>; clock-output-names = "pclk_peri_pre"; rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>; rockchip,div-relations = <0x0 1 0x1 2 0x2 4 0x3 8>; #clock-cells = <0>; #clock-init-cells = <1>; }; aclk_peri: aclk_peri_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>; clock-output-names = "aclk_peri"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con11: sel-con@0070 { compatible = "rockchip,rk3188-selcon"; reg = <0x0070 0x4>; #address-cells = <1>; #size-cells = <1>; clk_sdmmc0_div: clk_sdmmc0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 6>; clocks = <&clk_sdmmc0>; clock-output-names = "clk_sdmmc0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>; }; clk_sdmmc0: clk_sdmmc0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>; clock-output-names = "clk_sdmmc0"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_sfc_div: clk_sfc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_sfc>; clock-output-names = "clk_sfc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>; }; /* reg[13]: reserved */ clk_sfc: clk_sfc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>; clock-output-names = "clk_sfc"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con12: sel-con@0074 { compatible = "rockchip,rk3188-selcon"; reg = <0x0074 0x4>; #address-cells = <1>; #size-cells = <1>; clk_sdio_div: clk_sdio_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 6>; clocks = <&clk_sdio>; clock-output-names = "clk_sdio"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>; }; clk_sdio: clk_sdio_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>; clock-output-names = "clk_sdio"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_emmc_div: clk_emmc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 6>; clocks = <&clk_emmc>; clock-output-names = "clk_emmc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>; }; clk_emmc: clk_emmc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>; clock-output-names = "clk_emmc"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con13: sel-con@0078 { compatible = "rockchip,rk3188-selcon"; reg = <0x0078 0x4>; #address-cells = <1>; #size-cells = <1>; clk_uart0_pll_div: clk_uart0_pll_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_uart0_pll>; clock-output-names = "clk_uart0_pll"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[7]: reserved */ clk_uart0: clk_uart0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>; clock-output-names = "clk_uart0"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[11:10]: reserved */ clk_uart0_pll: clk_uart0_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <12 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>; clock-output-names = "clk_uart0_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_uart2_pll: clk_uart2_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>; clock-output-names = "clk_uart2_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con14: sel-con@007c { compatible = "rockchip,rk3188-selcon"; reg = <0x007c 0x4>; #address-cells = <1>; #size-cells = <1>; clk_uart1_div: clk_uart1_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_uart2_pll>; clock-output-names = "clk_uart1_div"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[7]: reserved */ clk_uart1: clk_uart1_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>; clock-output-names = "clk_uart1"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[15:10]: reserved */ }; clk_sel_con15: sel-con@0080 { compatible = "rockchip,rk3188-selcon"; reg = <0x0080 0x4>; #address-cells = <1>; #size-cells = <1>; clk_uart2_div: clk_uart2_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_uart2_pll>; clock-output-names = "clk_uart2_div"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[7]: reserved */ clk_uart2: clk_uart2_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>; clock-output-names = "clk_uart2"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[15:10]: reserved */ }; clk_sel_con17: sel-con@0088 { compatible = "rockchip,rk3188-selcon"; reg = <0x0088 0x4>; #address-cells = <1>; #size-cells = <1>; uart0_frac: uart0_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&clk_uart0_pll>; clock-output-names = "uart0_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con18: sel-con@008c { compatible = "rockchip,rk3188-selcon"; reg = <0x008c 0x4>; #address-cells = <1>; #size-cells = <1>; uart1_frac: uart1_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&clk_uart1_div>; clock-output-names = "uart1_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con19: sel-con@0090 { compatible = "rockchip,rk3188-selcon"; reg = <0x0090 0x4>; #address-cells = <1>; #size-cells = <1>; uart2_frac: uart2_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&clk_uart2_div>; clock-output-names = "uart2_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con20: sel-con@0094 { compatible = "rockchip,rk3188-selcon"; reg = <0x0094 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_frac: spdif_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&spdif_div>; clock-output-names = "spdif_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con23: sel-con@00a0 { compatible = "rockchip,rk3188-selcon"; reg = <0x00a0 0x4>; #address-cells = <1>; #size-cells = <1>; dclk_ebc: dclk_ebc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>; clock-output-names = "dclk_ebc"; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7:2]: reserved */ dclk_ebc_div: dclk_ebc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 8>; clocks = <&dclk_ebc>; clock-output-names = "dclk_ebc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; }; clk_sel_con24: sel-con@00a4 { compatible = "rockchip,rk3188-selcon"; reg = <0x00a4 0x4>; #address-cells = <1>; #size-cells = <1>; clk_crypto_div: clk_crypto_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 2>; clocks = <&aclk_cpu>; clock-output-names = "clk_crypto"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7:2]: reserved */ clk_saradc: clk_saradc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 8>; clocks = <&xin24m>; clock-output-names = "clk_saradc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con25: sel-con@00a8 { compatible = "rockchip,rk3188-selcon"; reg = <0x00a8 0x4>; #address-cells = <1>; #size-cells = <1>; clk_spi0_div: clk_spi0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spi0>; clock-output-names = "clk_spi0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[7]: reserved */ clk_spi0: clk_spi0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>; clock-output-names = "clk_spi0"; #clock-cells = <0>; }; /* reg[15:10]: reserved */ }; clk_sel_con26: sel-con@00ac { compatible = "rockchip,rk3188-selcon"; reg = <0x00ac 0x4>; #address-cells = <1>; #size-cells = <1>; ddr_div: ddr_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 2>; clocks = <&clk_ddr>; clock-output-names = "clk_ddr"; rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>; rockchip,div-relations = <0x0 1 0x1 2 0x3 4>; #clock-cells = <0>; rockchip,flags = <(CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)>; rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>; }; /* reg[7:2]: reserved */ clk_ddr: ddr_clk_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 1>; clocks = <&clk_dpll>, <&dummy>; clock-output-names = "clk_ddr"; #clock-cells = <0>; }; /* reg[15:9]: reserved */ }; clk_sel_con27: sel-con@00b0 { compatible = "rockchip,rk3188-selcon"; reg = <0x00b0 0x4>; #address-cells = <1>; #size-cells = <1>; dclk_lcdc0: dclk_lcdc0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>; clock-output-names = "dclk_lcdc0"; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7:2]: reserved */ dclk_lcdc0_div: dclk_lcdc0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 8>; clocks = <&dclk_lcdc0>; clock-output-names = "dclk_lcdc0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; }; clk_sel_con28: sel-con@00b4 { compatible = "rockchip,rk3188-selcon"; reg = <0x00b4 0x4>; #address-cells = <1>; #size-cells = <1>; sclk_lcdc0: sclk_lcdc0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>; clock-output-names = "sclk_lcdc0"; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7:2]: reserved */ sclk_lcdc0_div: sclk_lcdc0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 8>; clocks = <&sclk_lcdc0>; clock-output-names = "sclk_lcdc0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; }; clk_sel_con29: sel-con@00b8 { compatible = "rockchip,rk3188-selcon"; reg = <0x00b8 0x4>; #address-cells = <1>; #size-cells = <1>; clk_cif_pll: clk_cif_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>; clock-output-names = "clk_cif_pll"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_cif_out_div: clk_cif_out_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <2 5>; clocks = <&clk_cif_out>; clock-output-names = "clk_cif_out"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; clk_cif_out: clk_cif_out_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&clk_cif_pll>, <&xin24m>; clock-output-names = "clk_cif_out"; #clock-cells = <0>; #clock-init-cells = <1>; }; pclk_pmu_pre: pclk_pmu_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 6>; clocks = <&clk_cpll>; clock-output-names = "pclk_pmu_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15:14]: reserved */ }; clk_sel_con30: sel-con@00bc { compatible = "rockchip,rk3188-selcon"; reg = <0x00bc 0x4>; #address-cells = <1>; #size-cells = <1>; clk_testout_div: clk_testout_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&dummy>; clock-output-names = "clk_testout"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[6:5]: reserved */ clk_cif0_in: clk_cif0_in_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&pclkin_cif>, <&pclkin_cif_inv>; clock-output-names = "clk_cif0_in"; #clock-cells = <0>; #clock-init-cells = <1>; }; hclk_vio_pre_div: hclk_vio_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&hclk_vio_pre>; clock-output-names = "hclk_vio_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; /* reg[13]: reserved */ hclk_vio_pre: hclk_vio_pre_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>; clock-output-names = "hclk_vio_pre"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con31: sel-con@00c0 { compatible = "rockchip,rk3188-selcon"; reg = <0x00c0 0x4>; #address-cells = <1>; #size-cells = <1>; aclk_vio0_pre_div: aclk_vio0_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&aclk_vio0_pre>; clock-output-names = "aclk_vio0_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; aclk_vio0_pre: aclk_vio0_pre_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <5 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "aclk_vio0_pre"; #clock-cells = <0>; #clock-init-cells = <1>; }; aclk_vio1_pre_div: aclk_vio1_pre_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&aclk_vio1_pre>; clock-output-names = "aclk_vio1_pre"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; aclk_vio1_pre: aclk_vio1_pre_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <13 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "aclk_vio1_pre"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con32: sel-con@00c4 { compatible = "rockchip,rk3188-selcon"; reg = <0x00c4 0x4>; #address-cells = <1>; #size-cells = <1>; clk_vepu_div: clk_vepu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_vepu>; clock-output-names = "clk_vepu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; clk_vepu: clk_vepu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <5 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "clk_vepu"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_vdpu_div: clk_vdpu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_vdpu>; clock-output-names = "clk_vdpu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; clk_vdpu: clk_vdpu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <13 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "clk_vdpu"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con34: sel-con@00cc { compatible = "rockchip,rk3188-selcon"; reg = <0x00cc 0x4>; #address-cells = <1>; #size-cells = <1>; clk_gpu_div: clk_gpu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_gpu>; clock-output-names = "clk_gpu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; clk_gpu: clk_gpu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <5 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "clk_gpu"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_hevc_core_div: clk_hevc_core_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_hevc_core>; clock-output-names = "clk_hevc_core"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_NO_REPARENT>; }; clk_hevc_core: clk_hevc_core_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <13 3>; clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>; clock-output-names = "clk_hevc_core"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; }; /* Gate control regs */ clk_gate_cons { compatible = "rockchip,rk-gate-cons"; #address-cells = <1>; #size-cells = <1>; ranges ; clk_gates0: gate-clk@00d0{ compatible = "rockchip,rk3188-gate-clk"; reg = <0x00d0 0x4>; clocks = <&clk_core>, <&dummy>, <&dummy>, <&aclk_cpu>, <&aclk_cpu>, <&aclk_cpu>, <&dummy>, <&clk_core>, <&dummy>, <&clk_i2s_2ch_pll>, <&i2s_2ch_frac>, <&hclk_vio_pre>, <&aclk_cpu>, <&clk_i2s_2ch_out>, <&clk_i2s_2ch>, <&dummy>; clock-output-names = "pclk_dbg", "aclk_cpu", /*clk_cpu_cpll*/ "reserved", "aclk_cpu_pre", "hclk_cpu_pre", "pclk_cpu_pre", "clk_core", "aclk_core_pre", "reserved", "clk_i2s_2ch_pll", "i2s_2ch_frac", "hclk_vio_pre", "clk_crypto", "clk_i2s_2ch_out", "clk_i2s_2ch", "clk_testout"; rockchip,suspend-clkgating-setting=<0x11ff 0x0>; #clock-cells = <1>; }; clk_gates1: gate-clk@00d4{ compatible = "rockchip,rk3188-gate-clk"; reg = <0x00d4 0x4>; clocks = <&clk_cpll>, <&dummy>, <&dummy>, <&jtag_tck>, <&aclk_vio1_pre>, <&xin12m>, <&xin12m>, <&clk_mac_pll>, <&clk_uart0_pll>, <&uart0_frac>, <&clk_uart1_div>, <&uart1_frac>, <&clk_uart2_div>, <&uart2_frac>, <&clk_tsp>, <&dummy>; clock-output-names = "pclk_pmu_pre", "reserved", "reserved", "clk_jtag", "aclk_vio1_pre", "clk_otgphy0", "clk_otgphy1", "clk_mac_pll", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_tsp", "reserved"; rockchip,suspend-clkgating-setting=<0x000f 0x0>; #clock-cells = <1>; }; clk_gates2: gate-clk@00d8 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00d8 0x4>; clocks = <&aclk_peri>, <&aclk_peri>, <&aclk_peri>, <&aclk_peri>, <&clk_mac_ref>, <&clk_mac_ref>, <&clk_mac_ref>, <&clk_mac_ref>, <&clk_saradc>, <&clk_spi0>, <&clk_spdif_pll>, <&clk_sdmmc0>, <&spdif_frac>, <&clk_sdio>, <&clk_emmc>, <&xin24m>; clock-output-names = "aclk_peri", "aclk_peri_pre", "hclk_peri_pre", "pclk_peri_pre", "clk_mac_ref", "clk_mac_refout", "clk_mac_rx", "clk_mac_tx", "clk_saradc", "clk_spi0", "clk_spdif_pll", "clk_sdmmc0", "spdif_frac", "clk_sdio", "clk_emmc", "clk_mipi_24m"; rockchip,suspend-clkgating-setting=<0x000f 0x0>; #clock-cells = <1>; }; clk_gates3: gate-clk@00dc { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00dc 0x4>; clocks = <&aclk_vio0_pre>, <&dclk_lcdc0>, <&sclk_lcdc0>, <&pclkin_cif>, <&dclk_ebc>, <&hclk_cpu_pre>, <&hclk_peri_pre>, <&clk_cif_pll>, <&pclk_cpu_pre>, <&clk_vepu>, <&clk_hevc_core>, <&clk_vdpu>, <&hclk_vdpu>, <&clk_gpu>, <&aclk_peri>, <&clk_sfc>; clock-output-names = "aclk_vio0_pre", "dclk_lcdc0", "sclk_lcdc0", "pclkin_cif", "dclk_ebc", "g_hclk_crypto", "g_hclk_em_peri", "clk_cif_pll", "g_pclk_hdmi", "clk_vepu", "clk_hevc_core", "clk_vdpu", "hclk_vdpu", "clk_gpu", "g_hclk_gps", "clk_sfc"; rockchip,suspend-clkgating-setting=<0x0060 0x0000>; #clock-cells = <1>; }; clk_gates4: gate-clk@00e0{ compatible = "rockchip,rk3188-gate-clk"; reg = <0x00e0 0x4>; clocks = <&hclk_peri_pre>, <&pclk_peri_pre>, <&aclk_peri>, <&aclk_peri>, <&clk_i2s_8ch_pll>, <&i2s_8ch_frac>, <&clk_i2s_8ch>, <&dummy>, <&dummy>, <&dummy>, <&aclk_cpu>, <&dummy>, <&aclk_cpu>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_hp_axi_matrix", "g_pp_axi_matrix", "g_aclk_cpu_peri", "g_ap_axi_matrix", "clk_i2s_8ch_pll", "i2s_8ch_frac", "clk_i2s_8ch", "reserved", "reserved", "reserved", "g_aclk_strc_sys", "reserved", /* Not use these ddr gates */ "g_aclk_intmem", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting = <0xff8f 0x0000>; #clock-cells = <1>; }; clk_gates5: gate-clk@00e4 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00e4 0x4>; clocks = <&pclk_cpu_pre>, <&aclk_peri>, <&pclk_peri_pre>, <&dummy>, <&pclk_cpu_pre>, <&dummy>, <&hclk_cpu_pre>, <&pclk_cpu_pre>, <&dummy>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&dummy>, <&hclk_peri_pre>, <&pclk_cpu_pre>, <&dummy>; clock-output-names = "g_pclk_mipiphy", "g_aclk_dmac", "g_pclk_efuse", "reserved", "g_pclk_grf", "reserved", "g_hclk_rom", "g_pclk_ddrupctl", "reserved", "g_hclk_nandc", "g_hclk_sdmmc0", "g_hclk_sdio", "reserved", "g_hclk_otg0", "g_pclk_acodec", "reserved"; rockchip,suspend-clkgating-setting = <0x00f0 0x0000>; #clock-cells = <1>; }; clk_gates6: gate-clk@00e8 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00e8 0x4>; clocks = <&aclk_vio0_niu>, <&hclk_vio_niu>, <&dummy>, <&dummy>, <&hclk_vio_niu>, <&aclk_vio0_niu>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&hclk_vio_niu>, <&aclk_vio0_niu>, <&hclk_vio_pre>, <&aclk_vio0_pre>, <&dummy>, <&dummy>; clock-output-names = "g_aclk_lcdc0", "g_hclk_lcdc0", "reserved", "reserved", "g_hclk_cif", "g_aclk_cif", "reserved", "reserved", "reserved", "reserved", "g_hclk_rga", "g_aclk_rga", "hclk_vio_niu", "aclk_vio0_niu", "reserved", "reserved"; rockchip,suspend-clkgating-setting = <0x0000 0x0000>; #clock-cells = <1>; }; clk_gates7: gate-clk@00ec { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00ec 0x4>; clocks = <&hclk_peri_pre>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&dummy>, <&dummy>, <&pclk_peri_pre>, <&dummy>, <&dummy>, <&pclk_peri_pre>, <&dummy>, <&pclk_peri_pre>, <&dummy>, <&pclk_peri_pre>, <&pclk_peri_pre>; clock-output-names = "g_hclk_emmc", "g_hclk_sfc", "g_hclk_i2s_2ch", "g_hclk_host", "g_hclk_i2s_8ch", "reserved", "reserved", "g_pclk_timer", "reserved", "reserved", "g_pclk_pwm", "reserved", "g_pclk_spi0", "reserved", "g_pclk_saradc", "g_pclk_wdt"; rockchip,suspend-clkgating-setting = <0x8480 0x0000>; #clock-cells = <1>; }; clk_gates8: gate-clk@00f0 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00f0 0x4>; clocks = <&pclk_peri_pre>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&dummy>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&dummy>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&pclk_peri_pre>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_pclk_uart0", "g_pclk_uart1", "g_pclk_uart2", "reserved", "g_pclk_i2c0", "g_pclk_i2c1", "g_pclk_i2c2", "g_pclk_i2c3", "reserved", "g_pclk_gpio0", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0xff0f 0x0000>; #clock-cells = <1>; }; clk_gates9: gate-clk@00f4 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00f4 0x4>; clocks = <&dummy>, <&dummy>, <&pclk_pmu_pre>, <&pclk_pmu_pre>, <&dummy>, <&hclk_vio_niu>, <&hclk_vio_niu>, <&hclk_vio_niu>, <&aclk_vio1_niu>, <&hclk_vio_niu>, <&aclk_vio1_pre>, <&dummy>, <&pclk_peri_pre>, <&hclk_peri_pre>, <&hclk_peri_pre>, <&aclk_peri>; clock-output-names = "reserved", "reserved", "g_pclk_pmu", "g_pclk_pmu_noc", "reserved", "g_hclk_vio_h2p", "g_pclk_mipi", "g_hclk_iep", "g_aclk_iep", "g_hclk_ebc", "aclk_vio1_niu", "reserved", "g_pclk_sim_card", "g_hclk_usb_peri", "g_hclk_pe_arbi", "g_aclk_peri_niu"; rockchip,suspend-clkgating-setting=<0xf00f 0x0>; #clock-cells = <1>; }; clk_gates10: gate-clk@00f8 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x00f8 0x4>; clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&hclk_peri_pre>, <&aclk_peri>, <&pclk_peri_pre>, <&hclk_peri_pre>, <&clk_tsp_in>, <&hclk_peri_pre>, <&clk_nandc>; clock-output-names = "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_clk_pvtm_func", "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "g_hclk_spdif", "g_aclk_gmac", "g_pclk_gmac", "g_hclk_tsp", "g_clkin0_tsp", "g_hclk_usbhost", "clk_nandc"; rockchip,suspend-clkgating-setting = <0x0000 0x0>; /* pwm logic vol */ #clock-cells = <1>; }; }; }; }; }; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; pclk_dbg_src: pclk_core_dbg_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <9 5>; clocks = <&clk_core>; clock-output-names = "pclk_dbg_src"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[15:14]: reserved */ }; clk_sel_con38: sel-con@00f8 { compatible = "rockchip,rk3188-selcon"; reg = <0x00f8 0x4>; #address-cells = <1>; #size-cells = <1>; clk_nandc0_div: clk_nandc0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_nandc0>; clock-output-names = "clk_nandc0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[6:5]: reserved */ clk_nandc0: clk_nandc0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_nandc0"; #clock-cells = <0>; }; clk_nandc1_div: clk_nandc1_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_nandc1>; clock-output-names = "clk_nandc1"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[14:13]: reserved */ clk_nandc1: clk_nandc1_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <15 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_nandc1"; #clock-cells = <0>; }; }; clk_sel_con39: sel-con@00fc { compatible = "rockchip,rk3188-selcon"; reg = <0x00fc 0x4>; #address-cells = <1>; #size-cells = <1>; clk_spi2_div: clk_spi2_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spi2>; clock-output-names = "clk_spi2"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; clk_spi2: clk_spi2_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_spi2"; #clock-cells = <0>; }; aclk_hevc_div: aclk_hevc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&aclk_hevc>; clock-output-names = "aclk_hevc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[13]: reserved */ aclk_hevc: aclk_hevc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "aclk_hevc"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con40: sel-con@0100 { compatible = "rockchip,rk3188-selcon"; reg = <0x0100 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_8ch_div: spdif_8ch_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spdif_pll>; clock-output-names = "spdif_8ch_div"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[7]: reserved */ clk_spdif_8ch: spdif_8ch_clk_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>; clock-output-names = "clk_spdif_8ch"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[11:10]: reserved */ hclk_hevc: hclk_hevc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <12 2>; clocks = <&aclk_hevc>; clock-output-names = "hclk_hevc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15:14]: reserved */ }; clk_sel_con41: sel-con@0104 { compatible = "rockchip,rk3188-selcon"; reg = <0x0104 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_8ch_frac: spdif_8ch_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&spdif_8ch_div>; clock-output-names = "spdif_8ch_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con42: sel-con@0108 { compatible = "rockchip,rk3188-selcon"; reg = <0x0108 0x4>; #address-cells = <1>; #size-cells = <1>; clk_hevc_cabac_div: clk_hevc_cabac_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_hevc_cabac>; clock-output-names = "clk_hevc_cabac"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[5]: reserved */ clk_hevc_cabac: clk_hevc_cabac_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "clk_hevc_cabac"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_hevc_core_div: clk_hevc_core_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_hevc_core>; clock-output-names = "clk_hevc_core"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[13]: reserved */ clk_hevc_core: clk_hevc_core_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "clk_hevc_core"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; }; /* Gate control regs */ clk_gate_cons { compatible = "rockchip,rk-gate-cons"; #address-cells = <1>; #size-cells = <1>; ranges ; clk_gates0: gate-clk@0160 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0160 0x4>; clocks = <&dummy>, <&clk_apll>, <&clk_gpll>, <&aclk_bus>, <&hclk_bus>, <&pclk_bus>, <&dummy>, <&aclk_bus>, <&clk_dpll>, <&clk_gpll>, <&clk_gpll>, <&clk_cpll>, <&xin24m>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /* do not use bit1 = "core_apll" */ "clk_arm_gpll", "g_aclk_bus", "hclk_bus", "pclk_bus", "reserved", "aclk_bus_2pmu", "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/ "reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/ "clk_acc_efuse", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>; #clock-cells = <1>; }; clk_gates1: gate-clk@0164 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0164 0x4>; clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&dummy>, <&dummy>, <&clk_uart0_pll>, <&uart0_frac>, <&clk_uart1_div>, <&uart1_frac>, <&clk_uart2_div>, <&uart2_frac>, <&clk_uart3_div>, <&uart3_frac>; clock-output-names = "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "reserved", "reserved", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_uart3_div", "uart3_frac"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates2: gate-clk@0168 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0168 0x4>; clocks = <&aclk_peri>, <&aclk_peri>, <&hclk_peri>, <&pclk_peri>, <&dummy>, <&clk_mac_pll>, <&clk_hsadc_pll>, <&clk_tsadc>, <&clk_saradc>, <&clk_spi0>, <&clk_spi1>, <&clk_spi2>, <&clk_uart4_div>, <&uart4_frac>, <&dummy>, <&dummy>; clock-output-names = "aclk_peri", "reserved", /*"g_aclk_periph",*/ "hclk_peri", "pclk_peri", "reserved", "clk_mac_pll", "clk_hsadc_pll", "clk_tsadc", "clk_saradc", "clk_spi0", "clk_spi1", "clk_spi2", "clk_uart4_div", "uart4_frac", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x000f 0x000f>; #clock-cells = <1>; }; clk_gates3: gate-clk@016c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x016c 0x4>; clocks = <&aclk_vio0>, <&dclk_lcdc0>, <&aclk_vio1>, <&dclk_lcdc1>, <&clk_rga>, <&aclk_rga>, <&ehci1phy_480m>, <&clk_cif_pll>, <&dummy>, <&clk_vepu>, <&dummy>, <&clk_vdpu>, <&clk_edp_24m>, <&clk_edp>, <&clk_isp>, <&clk_isp_jpe>; clock-output-names = "aclk_vio0", "dclk_lcdc0", "aclk_vio1", "dclk_lcdc1", "clk_rga", "aclk_rga", "ehci1phy_480m", "clk_cif_pll", /*Not use hclk_vpu_gate tmp, fixme*/ "reserved", "clk_vepu", "reserved", "clk_vdpu", "clk_edp_24m", "clk_edp", "clk_isp", "clk_isp_jpe"; rockchip,suspend-clkgating-setting=<0x0000 0x0000>; #clock-cells = <1>; }; clk_gates4: gate-clk@0170 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0170 0x4>; clocks = <&clk_i2s_out>, <&clk_i2s_pll>, <&i2s_frac>, <&clk_i2s>, <&spdif_div>, <&spdif_frac>, <&clk_spdif>, <&spdif_8ch_div>, <&spdif_8ch_frac>, <&clk_spdif_8ch>, <&clk_tsp>, <&clk_tspout>, <&clk_ddr>, <&clk_ddr>, <&jtag_clkin>, <&dummy>; clock-output-names = "clk_i2s_out", "clk_i2s_pll", "i2s_frac", "clk_i2s", "spdif_div", "spdif_frac", "clk_spdif", "spdif_8ch_div", "spdif_8ch_frac", "clk_spdif_8ch", "clk_tsp", "clk_tspout", /* Not use these ddr gates */ "reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/ "clk_jtag", "reserved"; /*"testclk_gate_en";*/ rockchip,suspend-clkgating-setting=<0xf000 0xf000>; #clock-cells = <1>; }; clk_gates5: gate-clk@0174 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0174 0x4>; clocks = <&clk_mac>, <&clk_mac>, <&clk_mac>, <&clk_mac>, <&clk_crypto>, <&clk_nandc0>, <&clk_nandc1>, <&clk_gpu>, <&pclk_pd_pmu>, <&xin24m>, <&xin24m>, <&xin32k>, <&xin24m>, <&xin24m>, <&usbphy_480m>, <&xin24m>; clock-output-names = "g_clk_mac_rx", "g_clk_mac_tx", "g_clk_mac_ref", "g_mac_refout", "clk_crypto", "clk_nandc0", "clk_nandc1", "clk_gpu", "pclk_pd_pmu", "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_hdmi_cec_clk", "g_hdmi_hdcp_clk", "g_ps2c_clk", "usbphy_480m", "g_mipidsi_24m"; rockchip,suspend-clkgating-setting=<0x0100 0x0100>; #clock-cells = <1>; }; clk_gates6: gate-clk@0178 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0178 0x4>; clocks = <&hclk_peri>, <&pclk_peri>, <&aclk_peri>, <&aclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&dummy>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>; clock-output-names = "g_hp_matrix", "g_pp_axi_matrix", "g_ap_axi_matrix", "g_aclk_dmac2", "g_pclk_spi0", "g_pclk_spi1", "g_pclk_spi2", "g_pclk_ps2c", "g_pclk_uart0", "g_pclk_uart1", "reserved", "g_pclk_uart3", "g_pclk_uart4", "g_pclk_i2c1", "g_pclk_i2c3", "g_pclk_i2c4"; rockchip,suspend-clkgating-setting=<0x0003 0x0003>; #clock-cells = <1>; }; clk_gates7: gate-clk@017c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x017c 0x4>; clocks = <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&aclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>; clock-output-names = "g_pclk_i2c5", "g_pclk_saradc", "g_pclk_tsadc", "g_pclk_sim", "g_hclk_otg0", "g_pmu_hclk_otg0", "g_hclk_host0", "g_hclk_host1", "g_hclk_ehci1", "g_hclk_usb_peri", "g_hp_ahb_arbi", "g_aclk_peri_niu", "g_h_emem_peri", "g_hclk_mem_peri", "g_hclk_nandc0", "g_hclk_nandc1"; rockchip,suspend-clkgating-setting=<0x0c00 0xc000>; #clock-cells = <1>; }; clk_gates8: gate-clk@0180 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0180 0x4>; clocks = <&aclk_peri>, <&pclk_peri>, <&aclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hsadc_0_tsp>, <&hsadc_1_tsp>, <&io_27m_in>, <&aclk_peri>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_aclk_gmac", "g_pclk_gmac", "g_hclk_gps", "g_hclk_sdmmc", "g_hclk_sdio0", "g_hclk_sdio1", "g_hclk_emmc", "g_hclk_hsadc", "g_hclk_tsp", "g_hsadc_0_tsp", "g_hsadc_1_tsp", "g_clk_27m_tsp", "g_aclk_peri_mmu", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0000 0x0000>; #clock-cells = <1>; }; clk_gates9: gate-clk@0184 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0184 0x4>; clocks = <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/ "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates10: gate-clk@0188 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0188 0x4>; clocks = <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&aclk_bus>, <&aclk_bus>, <&aclk_bus>, <&aclk_bus>, <&hclk_bus>, <&hclk_bus>, <&hclk_bus>, <&hclk_bus>, <&aclk_bus>, <&aclk_bus>, <&pclk_bus>, <&pclk_bus>; clock-output-names = "g_pclk_pwm", "g_pclk_timer", "g_pclk_i2c0", "g_pclk_i2c2", "g_aclk_intmem", "g_clk_intmem0", "g_clk_intmem1", "g_clk_intmem2", "g_hclk_i2s", "g_hclk_rom", "g_hclk_spdif", "g_h_spdif_8ch", "g_aclk_dmac1", "g_aclk_strc_sys", "reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/ //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol #clock-cells = <1>; }; clk_gates11: gate-clk@018c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x018c 0x4>; clocks = <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&dummy>, <&dummy>, <&aclk_bus>, <&hclk_bus>, <&aclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/ "g_p_efuse_1024", "g_pclk_tzpc", "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/ "g_aclk_crypto", "g_hclk_crypto", "g_aclk_ccp", "g_pclk_uart2", "g_p_efuse_256", "g_pclk_rkpwm", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0033 0x0033>; #clock-cells = <1>; }; clk_gates12: gate-clk@0190 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0190 0x4>; clocks = <&clk_core0>, <&clk_core1>, <&clk_core2>, <&clk_core3>, <&clk_l2ram>, <&aclk_core_m0>, <&aclk_core_mp>, <&atclk_core>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "clk_core0", "clk_core1", "clk_core2", "clk_core3", "clk_l2ram", "aclk_core_m0", "aclk_core_mp", "atclk_core", "pclk_dbg_src", "g_dbg_core_clk", "g_cs_dbg_clk", "g_pclk_core_niu", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>; #clock-cells = <1>; }; clk_gates13: gate-clk@0194 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0194 0x4>; clocks = <&clk_sdmmc>, <&clk_sdio0>, <&clk_sdio1>, <&clk_emmc>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin32k>, <&aclk_bus_src>, <&xin12m>, <&xin24m>, <&xin24m>, <&dummy>, <&aclk_hevc>, <&clk_hevc_cabac>, <&clk_hevc_core>; clock-output-names = "clk_sdmmc", "clk_sdio0", "clk_sdio1", "clk_emmc", "clk_otgphy0", "clk_otgphy1", "clk_otgphy2", "clk_otg_adp", "g_clk_c2c_host", "g_clk_ehci1_12m", "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", "g_clk_wifi", "aclk_hevc", "clk_hevc_cabac", "clk_hevc_core"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates14: gate-clk@0198 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0198 0x4>; clocks = <&dummy>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&dummy>, <&dummy>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "g_pclk_gpio4", "g_pclk_gpio5", "g_pclk_gpio6", "g_pclk_gpio7", "g_pclk_gpio8", "reserved", "reserved", "g_pclk_grf", "g_p_alive_niu", "reserved", "reserved", "reserved"; //rockchip,suspend-clkgating-setting=<0xffff 0xffff>; rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>; #clock-cells = <1>; }; clk_gates15: gate-clk@019c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x019c 0x4>; clocks = <&aclk_rga>, <&hclk_vio>, <&clk_gates15 11>, <&hclk_vio>, <&dummy>, <&clk_gates15 11>, <&hclk_vio>, <&clk_gates15 12>, <&hclk_vio>, <&dummy>, <&dummy>, <&aclk_vio0>, <&aclk_vio1>, <&aclk_rga>, <&clk_gates15 11>, <&hclk_vio>; clock-output-names = "reserved", /*"g_aclk_rga"*/ "g_hclk_rga", "g_aclk_iep", "g_hclk_iep", "g_aclk_lcdc_iep", "g_aclk_lcdc0", "g_hclk_lcdc0", "g_aclk_lcdc1", "g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */ "reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu", "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/ "g_aclk_vip", "g_hclk_vip"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates16: gate-clk@01a0 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a0 0x4>; clocks = <&pclkin_cif>, <&hclk_vio>, <&clk_gates15 12>, <&pclkin_isp>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_pclkin_cif", "g_hclk_isp", "g_aclk_isp", "g_pclkin_isp", "g_p_mipi_dsi0", "g_p_mipi_dsi1", "g_p_mipi_csi", "g_pclk_lvds_phy", "g_pclk_edp_ctrl", "g_p_hdmi_ctrl", "reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */ "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates17: gate-clk@01a4 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a4 0x4>; clocks = <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_pclk_pmu", "g_pclk_intmem1", "g_pclk_pmu_niu", "g_pclk_sgrf", "g_pclk_gpio0", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x01f 0x01f>; #clock-cells = <1>; }; clk_gates18: gate-clk@01a8 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a8 0x4>; clocks = <&clk_gpu>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", /*"g_aclk_gpu",*/ "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; }; }; }; };