关键词：rk3288-pinctrl.dtsi ,linux_3.10,rockchip,dts
dts — rk3288-pinctrl.dtsi
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pinctrl/rockchip-rk3288.h>
/ {
pinctrl: pinctrl@ff770000 {
compatible = "rockchip,rk3288-pinctrl";
reg = <0xff770000 0x140>,
<0xff770140 0x80>,
<0xff7701c0 0x80>;
reg-names = "base", "pull", "drv";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@ff750000 {
compatible = "rockchip,rk3288-gpio-bank0";
reg = <0xff750000 0x100>,
<0xff730084 0x0c>,
<0xff730064 0x0c>,
<0xff730070 0x0c>;
reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates17 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0xff780000 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0xff790000 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7a0000 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio4@ff7b0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7b0000 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio5@ff7c0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7c0000 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio6@ff7d0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7d0000 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio7@ff7e0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7e0000 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 7>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio8@ff7f0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7f0000 0x100>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio15: gpio15@ff7f2000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7f2000 0x100>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;//127 = 160-32-1
clocks = <&clk_gates14 8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
};
pcfg_pull_down: pcfg_pull_down {
bias-pull-down;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
gpio4_uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <UART0BT_SIN>,
<UART0BT_SOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart0_cts: uart0-cts {
rockchip,pins = <UART0BT_CTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart0_rts: uart0-rts {
rockchip,pins = <UART0BT_RTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart0_rts_gpio: uart0-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART0BT_RTSN)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio5_uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <UART1BB_SIN>,
<UART1BB_SOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart1_cts: uart1-cts {
rockchip,pins = <UART1BB_CTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart1_rts: uart1-rts {
rockchip,pins = <UART1BB_RTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart1_rts_gpio: uart1-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART1BB_RTSN)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio7_uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <UART2DBG_SIN>,
<UART2DBG_SOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
/* no rts / cts for uart2 */
};
gpio7_uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <UART3GPS_SIN>,
<UART3GPS_SOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart3_cts: uart3-cts {
rockchip,pins = <UART3GPS_CTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart3_rts: uart3-rts {
rockchip,pins = <UART3GPS_RTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio5_uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins = <UART4EXP_SIN>,
<UART4EXP_SOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart4_cts: uart4-cts {
rockchip,pins = <UART4EXP_CTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
uart4_rts: uart4-rts {
rockchip,pins = <UART4EXP_RTSN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio0_i2c0 {
i2c0_sda:i2c0-sda {
rockchip,pins = <I2C0PMU_SDA>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c0_scl:i2c0-scl {
rockchip,pins = <I2C0PMU_SCL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c0_gpio: i2c0-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C0PMU_SDA)>, <FUNC_TO_GPIO(I2C0PMU_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio8_i2c1 {
i2c1_sda:i2c1-sda {
rockchip,pins = <I2C1SENSOR_SDA>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c1_scl:i2c1-scl {
rockchip,pins = <I2C1SENSOR_SCL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c1_gpio: i2c1-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C1SENSOR_SDA)>, <FUNC_TO_GPIO(I2C1SENSOR_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio6_i2c2 {
i2c2_sda:i2c2-sda {
rockchip,pins = <I2C2AUDIO_SDA>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c2_scl:i2c2-scl {
rockchip,pins = <I2C2AUDIO_SCL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c2_gpio: i2c2-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C2AUDIO_SDA)>, <FUNC_TO_GPIO(I2C2AUDIO_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio2_i2c3 {
i2c3_sda:i2c3-sda {
rockchip,pins = <I2C3CAM_SDA>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c3_scl:i2c3-scl {
rockchip,pins = <I2C3CAM_SCL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c3_gpio: i2c3-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C3CAM_SDA)>, <FUNC_TO_GPIO(I2C3CAM_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio7_i2c4 {
i2c4_sda:i2c4-sda {
rockchip,pins = <I2C4TP_SDA>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c4_scl:i2c4-scl {
rockchip,pins = <I2C4TP_SCL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c4_gpio: i2c4-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C4TP_SDA)>, <FUNC_TO_GPIO(I2C4TP_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio7_i2c5 {
i2c5_sda:i2c5-sda {
rockchip,pins = <EDPHDMII2C_SDA>;
rockchip,pull = <VALUE_PULL_NORMAL>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c5_scl:i2c5-scl {
rockchip,pins = <EDPHDMII2C_SCL>;
rockchip,pull = <VALUE_PULL_NORMAL>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2c5_gpio: i2c5-gpio {
rockchip,pins = <FUNC_TO_GPIO(EDPHDMII2C_SDA)>, <FUNC_TO_GPIO(EDPHDMII2C_SCL)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio5_spi0 {
spi0_txd:spi0-txd {
rockchip,pins = <SPI0_TXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi0_rxd:spi0-rxd {
rockchip,pins = <SPI0_RXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi0_clk:spi0-clk {
rockchip,pins = <SPI0_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi0_cs0:spi0-cs0 {
rockchip,pins = <SPI0_CS0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi0_cs1:spi0-cs1 {
rockchip,pins = <SPI0_CS1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio7_spi1 {
spi1_txd:spi1-txd {
rockchip,pins = <SPI1_TXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi1_rxd:spi1-rxd {
rockchip,pins = <SPI1_RXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi1_clk:spi1-clk {
rockchip,pins = <SPI1_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi1_cs0:spi1-cs0 {
rockchip,pins = <SPI1_CS0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio8_spi2 {
spi2_txd:spi2-txd {
rockchip,pins = <SPI2_TXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_rxd:spi2-rxd {
rockchip,pins = <SPI2_RXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_clk:spi2-clk {
rockchip,pins = <SPI2_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_cs0:spi2-cs0 {
rockchip,pins = <SPI2_CS0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_cs1:spi2-cs1 {
rockchip,pins = <SPI2_CS1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio6_i2s {
i2s_mclk:i2s-mclk {
rockchip,pins = <I2S_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sclk:i2s-sclk {
rockchip,pins = <I2S_SCLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_lrckrx:i2s-lrckrx {
rockchip,pins = <I2S_LRCKRX>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_lrcktx:i2s-lrcktx {
rockchip,pins = <I2S_LRCKTX>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sdo0:i2s-sdo0 {
rockchip,pins = <I2S_SDO0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sdo1:i2s-sdo1 {
rockchip,pins = <I2S_SDO1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sdo2:i2s-sdo2 {
rockchip,pins = <I2S_SDO2>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sdo3:i2s-sdo3 {
rockchip,pins = <I2S_SDO3>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_sdi:i2s-sdi {
rockchip,pins = <I2S_SDI>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
i2s_gpio: i2s-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2S_CLK)>,
<FUNC_TO_GPIO(I2S_SCLK)>,
<FUNC_TO_GPIO(I2S_LRCKRX)>,
<FUNC_TO_GPIO(I2S_LRCKTX)>,
<FUNC_TO_GPIO(I2S_SDO0)>,
<FUNC_TO_GPIO(I2S_SDO1)>,
<FUNC_TO_GPIO(I2S_SDO2)>,
<FUNC_TO_GPIO(I2S_SDO3)>,
<FUNC_TO_GPIO(I2S_SDI)>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio1_lcdc0 {
lcdc0_lcdc:lcdc0-lcdc {
rockchip,pins =
<LCDC0_DCLK_GPIO1D>,
<LCDC0_DEN_GPIO1D>,
<LCDC0_HSYNC_GPIO1D>,
<LCDC0_VSYNC_GPIO1D>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
lcdc0_gpio:lcdc0-gpio {
rockchip,pins =
<FUNC_TO_GPIO(LCDC0_DCLK_GPIO1D)>,
<FUNC_TO_GPIO(LCDC0_DEN_GPIO1D)>,
<FUNC_TO_GPIO(LCDC0_HSYNC_GPIO1D)>,
<FUNC_TO_GPIO(LCDC0_VSYNC_GPIO1D)>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio6_spdif {
spdif_tx: spdif-tx {
rockchip,pins = <SPDIF_TX>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio7_pwm {
vop0_pwm_pin:vop0-pwm {
rockchip,pins = <VOP0_PWM>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
vop1_pwm_pin:vop1-pwm {
rockchip,pins = <VOP1_PWM>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
pwm0_pin:pwm0 {
rockchip,pins = <PWM0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
pwm1_pin:pwm1 {
rockchip,pins = <PWM1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
pwm2_pin:pwm2 {
rockchip,pins = <PWM2>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
pwm3_pin:pwm3 {
rockchip,pins = <PWM3>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio3_emmc0 {
emmc0_clk: emmc0-clk {
rockchip,pins = <EMMC_CLKOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_8MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
emmc0_cmd: emmc0-cmd {
rockchip,pins = <EMMC_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_8MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
emmc0_rstnout: emmc0-rstnout {
rockchip,pins = <EMMC_RSTNOUT>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_8MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
emmc0_pwr: emmc0-pwr {
rockchip,pins = <EMMC_PWREN>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
emmc0_bus1: emmc0-bus-width1 {
rockchip,pins = <EMMC_DATA0>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_8MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
emmc0_bus4: emmc0-bus-width4 {
rockchip,pins = <EMMC_DATA0>,
<EMMC_DATA1>,
<EMMC_DATA2 >,
<EMMC_DATA3>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_8MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio6_sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
rockchip,pins = <SDMMC0_CLKOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins = <SDMMC0_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdmmc0_dectn: sdmmc0-dectn{
rockchip,pins = <SDMMC0_DECTN>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdmmc0_bus1: sdmmc0-bus-width1 {
rockchip,pins = <SDMMC0_DATA0>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdmmc0_bus4: sdmmc0-bus-width4 {
rockchip,pins = <SDMMC0_DATA0>,
<SDMMC0_DATA1>,
<SDMMC0_DATA2>,
<SDMMC0_DATA3>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdmmc0_gpio: sdmmc0_gpio{
rockchip,pins =
<GPIO6_C4>, //CMD
<GPIO6_C5>, //CLK
<GPIO6_C6>, //DET
<GPIO6_C0>, //D0
<GPIO6_C1>, //D1
<GPIO6_C2>, //D2
<GPIO6_C3>; //D3
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio4_sdio0 {
sdio0_clk: sdio0_clk {
rockchip,pins = <SDIO0_CLKOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_cmd: sdio0_cmd {
rockchip,pins = <SDIO0_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_dectn: sdio0-dectn{
rockchip,pins = <SDIO0_DETECTN>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_wrprt: sdio0_wrprt{
rockchip,pins = <SDIO0_WRPRT>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_pwr: sdio0-pwren{
rockchip,pins = <SDIO0_PWREN>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_bkpwr: sdio0-bkpwr{
rockchip,pins = <SDIO0_BKPWR>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_intn: sdio0-intn{
rockchip,pins = <SDIO0_INTN>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_bus1: sdio0-bus-width1 {
rockchip,pins = <SDIO0_DATA0>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_bus4: sdio0-bus-width4 {
rockchip,pins = <SDIO0_DATA0>,
<SDIO0_DATA1>,
<SDIO0_DATA2>,
<SDIO0_DATA3>;
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
sdio0_gpio: sdio0-all-gpio{
rockchip,pins =
<GPIO4_D1>, //CLK
<GPIO4_D0>, //CMD
<GPIO4_D2>, //DET
<GPIO4_D3>, //wrprt
<GPIO4_D4>, //PWREN
<GPIO4_D5>, //BKPWR
<GPIO4_D6>, //DO
<GPIO4_C4>, //D1
<GPIO4_C5>, //D2
<GPIO4_C6>, //D3
<GPIO4_C7>; //INTN
rockchip,pull = <VALUE_PULL_UP>;
rockchip,drive = <VALUE_DRV_4MA>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio2_gps {
gps_mag:gps-mag {
rockchip,pins = <GPS_MAG>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
gps_sig:gps-sig {
rockchip,pins = <GPS_SIG>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
gps_rfclk:gps-rfclk {
rockchip,pins = <GPS_RFCLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio4_gmac {
mac_clk: mac-clk {
rockchip,pins = <MAC_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
mac_txpins: mac-txpins {
rockchip,pins = <MAC_TXD0>, <MAC_TXD1>, <MAC_TXD2>, <MAC_TXD3>, <MAC_TXEN>, <MAC_TXCLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
mac_rxpins: mac-rxpins {
rockchip,pins = <MAC_RXD0>, <MAC_RXD1>, <MAC_RXD2>, <MAC_RXD3>, <MAC_RXDV>, <MAC_RXER>, <MAC_RXCLK>, <MAC_COL>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
mac_crs: mac-crs {
rockchip,pins = <MAC_CRS>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
mac_mdpins: mac-mdpins {
rockchip,pins = <MAC_MDIO>, <MAC_MDC>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio0_tsadc: gpio0-tsadc {
tsadc_int: tsadc-int {
rockchip,pins = <TSADC_INT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
};
tsadc_gpio: tsadc-gpio {
rockchip,pins = <GPIO0_B2>;
rockchip,pull = <VALUE_PULL_DISABLE>;
};
};
gpio7_cec {
hdmi_cec: hdmi-cec {
rockchip,pins = <EDPHDMI_CECINOUTRESERVED>;
rockchip,pull = <VALUE_PULL_NORMAL>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_cec_gpio: hdmi-cec-gpio {
rockchip,pins = <FUNC_TO_GPIO(EDPHDMI_CECINOUTRESERVED)>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
//to add
vol_domain{
//default 3.3V
lcdc_vcc:lcdc-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
dvp_vcc:dvp-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
flash0_vcc:flash0-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
flash1_vcc:flash1-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
wifi_vcc:wifi-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
bb_vcc:bb-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
audio_vcc:audio-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
sdcard_vcc:sdcard-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
gpio30_vcc:gpio30-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
gpio1830_vcc:gpio1830-vcc {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
rockchip,voltage = <VALUE_VOL_DEFAULT>;
};
//1.8V
lcdc_vcc_18:lcdc-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
dvp_vcc_18:dvp-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
flash0_vcc_18:flash0-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
flash1_vcc_18:flash1-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
wifi_vcc_18:wifi-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
bb_vcc_18:bb-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
audio_vcc_18:audio-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
sdcard_vcc_18:sdcard-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
gpio30_vcc_18:gpio30-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
gpio1830_vcc_18:gpio1830-vcc-18 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
rockchip,voltage = <VALUE_VOL_1V8>;
};
//3.3V
lcdc_vcc_33:lcdc-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
dvp_vcc_33:dvp-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
flash0_vcc_33:flash0-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
flash1_vcc_33:flash1-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
wifi_vcc_33:wifi-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
bb_vcc_33:bb-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
audio_vcc_33:audio-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
sdcard_vcc_33:sdcard-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
gpio30_vcc_33:gpio30-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
gpio1830_vcc_33:gpio1830-vcc-33 {
rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
rockchip,voltage = <VALUE_VOL_3V3>;
};
};
isp_pin {
isp_mipi:isp_mipi{
rockchip,pins = <CIF_CLKOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_dvp_d2d9:isp_dvp_d2d9 {
rockchip,pins = <CIF_DATA2>,<CIF_DATA3>,
<CIF_DATA4>,<CIF_DATA5>,
<CIF_DATA6>,<CIF_DATA7>,
<CIF_DATA8>,<CIF_DATA9>,
<CIF_VSYNC>,<CIF_HREF>,
<CIF_CLKIN>,<CIF_CLKOUT>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_dvp_d0d1:isp_d0d1 {
rockchip,pins = <CIF_DATA0>,<CIF_DATA1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_dvp_d10d11:isp_d10d11 {
rockchip,pins = <CIF_DATA10>,<CIF_DATA11>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_dvp_d0d7:isp_d0d7 {
rockchip,pins = <CIF_DATA0>,<CIF_DATA1>,
<CIF_DATA2>,<CIF_DATA3>,
<CIF_DATA4>,<CIF_DATA5>,
<CIF_DATA6>,<CIF_DATA7>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_shutter:isp_shutter {
rockchip,pins = <ISP_SHUTTEREN>,<ISP_SHUTTERTRIG>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_flash_trigger:isp_flash_trigger {
rockchip,pins = <ISP_FLASHTRIGOUTSPI1_CS0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_prelight:isp_prelight {
rockchip,pins = <ISP_PRELIGHTTRIGSPI1_RXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
isp_flash_trigger_as_gpio:isp_flash_trigger_as_gpio {
rockchip,pins = <FUNC_TO_GPIO(ISP_FLASHTRIGOUTSPI1_CS0)>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
};
};
ult>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>,
<1 RK_PD4 2 &pcfg_pull_default>,
<1 RK_PD5 2 &pcfg_pull_default>,
<1 RK_PD6 2 &pcfg_pull_default>,
<1 RK_PD7 2 &pcfg_pull_default>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
<2 RK_PC5 3 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
<0 RK_PA7 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
<2 RK_PD3 2 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
<1 RK_PB2 2 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
sdmmc_wp: sdmmc-wp {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
<1 RK_PC3 1 &pcfg_pull_default>,
<1 RK_PC4 1 &pcfg_pull_default>,
<1 RK_PC5 1 &pcfg_pull_default>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
};
sdio_pwren: sdio-pwren {
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
<1 RK_PA2 2 &pcfg_pull_default>,
<1 RK_PA4 2 &pcfg_pull_default>,
<1 RK_PA5 2 &pcfg_pull_default>;
};
};
hdmi {
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
<0 RK_PA7 2 &pcfg_pull_none>;
};
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s {
i2s_bus: i2s-bus {
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
<0 RK_PB1 1 &pcfg_pull_none>,
<0 RK_PB3 1 &pcfg_pull_none>,
<0 RK_PB4 1 &pcfg_pull_none>,
<0 RK_PB5 1 &pcfg_pull_none>,
<0 RK_PB6 1 &pcfg_pull_none>;
};
i2s1_bus: i2s1-bus {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
<1 RK_PA1 1 &pcfg_pull_none>,
<1 RK_PA2 1 &pcfg_pull_none>,
<1 RK_PA3 1 &pcfg_pull_none>,
<1 RK_PA4 1 &pcfg_pull_none>,
<1 RK_PA5 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB1 3 &pcfg_pull_default>,
<2 RK_PB3 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC2 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>,
<2 RK_PC4 4 &pcfg_pull_default>,
<2 RK_PC5 4 &pcfg_pull_default>,
<2 RK_PC6 4 &pcfg_pull_default>,
<2 RK_PC7 4 &pcfg_pull_default>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PB7 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PC4 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
};
};
spi {
spi0_clk: spi0-clk {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
};
spi0_tx: spi0-tx {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
};
spi0_rx: spi0-rx {
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
};
spi1_clk: spi1-clk {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
};
spi1_tx: spi1-tx {
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
};
spi1_rx: spi1-rx {
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
};
spi2_clk: spi2-clk {
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
};
spi2_tx: spi2-tx {
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
};
spi2_rx: spi2-rx {
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
};
};
};
};
-cells = <1>;
};
/* reg[14:13]: reserved */
clk_edp_24m: edp_24m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&edp_24m_clkin>, <&xin24m>;
clock-output-names = "clk_edp_24m";
#clock-cells = <0>;
};
};
clk_sel_con29: sel-con@00d4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ehci1phy_480m: ehci1phy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "ehci1phy_480m";
#clock-cells = <0>;
};
ehci1phy_12m: ehci1phy_12m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
clock-output-names = "ehci1phy_12m";
#clock-cells = <0>;
};
clkin_isp: clkin_isp {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <3 1>;
clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
clock-output-names = "clkin_isp";
#clock-cells = <0>;
};
clkin_cif: clkin_cif {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
clock-output-names = "clkin_cif";
#clock-cells = <0>;
};
/* reg[5]: reserved */
dclk_lcdc1: dclk_lcdc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc1";
#clock-cells = <0>;
};
dclk_lcdc1_div: dclk_lcdc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc1>;
clock-output-names = "dclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC1>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con30: sel-con@00d8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_rga_div: aclk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_rga>;
clock-output-names = "aclk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_rga_div: clk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_rga>;
clock-output-names = "clk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con31: sel-con@00dc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00dc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_vio0_div: aclk_vio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_vio0>;
clock-output-names = "aclk_vio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[5]: reserved */
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_vio1_div: aclk_vio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_vio1>;
clock-output-names = "aclk_vio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00e0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_vepu_div: clk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_vdpu_div: clk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con33: sel-con@00e4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
pclk_pd_pmu: pclk_pd_pmu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_pmu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
pclk_pd_alive: pclk_pd_alive {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_alive";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:13]: reserved */
};
clk_sel_con34: sel-con@00e8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_sdio1_div: clk_sdio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_sdio1>;
clock-output-names = "clk_sdio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
};
clk_sel_con35: sel-con@00ec {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ec 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_tsp_div: clk_tsp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_tsp>;
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_tspout_div: clk_tspout_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_tspout>;
clock-output-names = "clk_tspout";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con36: sel-con@00f0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_core0: clk_core0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
clk_core1: clk_core1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[7]: reserved */
clk_core2: clk_core2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[11]: reserved */
clk_core3: clk_core3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core3";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15]: reserved */
};
clk_sel_con37: sel-con@00f4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_l2ram: clk_l2ram_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_l2ram";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
atclk_core: atclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 5>;
clocks = <&clk_core>;
clock-output-names = "atclk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
pclk_dbg_src: pclk_core_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg_src";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15:14]: reserved */
};
clk_sel_con38: sel-con@00f8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_nandc0_div: clk_nandc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_nandc0>;
clock-output-names = "clk_nandc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[6:5]: reserved */
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1_div: clk_nandc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_nandc1>;
clock-output-names = "clk_nandc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14:13]: reserved */
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
};
clk_sel_con39: sel-con@00fc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00fc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi2_div: clk_spi2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi2>;
clock-output-names = "clk_spi2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
aclk_hevc_div: aclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_hevc>;
clock-output-names = "aclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con40: sel-con@0100 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0100 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_div: spdif_8ch_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spdif_pll>;
clock-output-names = "spdif_8ch_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif_8ch: spdif_8ch_clk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
clock-output-names = "clk_spdif_8ch";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
hclk_hevc: hclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_hevc>;
clock-output-names = "hclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:14]: reserved */
};
clk_sel_con41: sel-con@0104 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0104 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_frac: spdif_8ch_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&spdif_8ch_div>;
clock-output-names = "spdif_8ch_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con42: sel-con@0108 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0108 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hevc_cabac_div: clk_hevc_cabac_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_hevc_cabac>;
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_hevc_core_div: clk_hevc_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_hevc_core>;
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@0160 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0160 0x4>;
clocks =
<&dummy>, <&clk_apll>,
<&clk_gpll>, <&aclk_bus>,
<&hclk_bus>, <&pclk_bus>,
<&dummy>, <&aclk_bus>,
<&clk_dpll>, <&clk_gpll>,
<&clk_gpll>, <&clk_cpll>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /* do not use bit1 = "core_apll" */
"clk_arm_gpll", "g_aclk_bus",
"hclk_bus", "pclk_bus",
"reserved", "aclk_bus_2pmu",
"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@0164 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0164 0x4>;
clocks =
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&clk_uart0_pll>, <&uart0_frac>,
<&clk_uart1_div>, <&uart1_frac>,
<&clk_uart2_div>, <&uart2_frac>,
<&clk_uart3_div>, <&uart3_frac>;
clock-output-names =
"clk_timer0", "clk_timer1",
"clk_timer2", "clk_timer3",
"clk_timer4", "clk_timer5",
"reserved", "reserved",
"clk_uart0_pll", "uart0_frac",
"clk_uart1_div", "uart1_frac",
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@0168 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0168 0x4>;
clocks =
<&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&dummy>, <&clk_mac_pll>,
<&clk_hsadc_pll>, <&clk_tsadc>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_spi2>,
<&clk_uart4_div>, <&uart4_frac>,
<&dummy>, <&dummy>;
clock-output-names =
"aclk_peri", "reserved", /*"g_aclk_periph",*/
"hclk_peri", "pclk_peri",
"reserved", "clk_mac_pll",
"clk_hsadc_pll", "clk_tsadc",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_spi2",
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@016c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x016c 0x4>;
clocks =
<&aclk_vio0>, <&dclk_lcdc0>,
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
<&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
<&clk_edp_24m>, <&clk_edp>,
<&clk_isp>, <&clk_isp_jpe>;
clock-output-names =
"aclk_vio0", "dclk_lcdc0",
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
"ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"reserved", "clk_vdpu",
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@0170 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
<&clk_i2s_out>, <&clk_i2s_pll>,
<&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&spdif_8ch_frac>, <&clk_spdif_8ch>,
<&clk_tsp>, <&clk_tspout>,
<&clk_ddr>, <&clk_ddr>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
"clk_i2s_out", "clk_i2s_pll",
"i2s_frac", "clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"spdif_8ch_frac", "clk_spdif_8ch",
"clk_tsp", "clk_tspout",
/* Not use these ddr gates */
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@0174 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0174 0x4>;
clocks =
<&clk_mac>, <&clk_mac>,
<&clk_mac>, <&clk_mac>,
<&clk_crypto>, <&clk_nandc0>,
<&clk_nandc1>, <&clk_gpu>,
<&pclk_pd_pmu>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&xin24m>, <&xin24m>,
<&usbphy_480m>, <&xin24m>;
clock-output-names =
"g_clk_mac_rx", "g_clk_mac_tx",
"g_clk_mac_ref", "g_mac_refout",
"clk_crypto", "clk_nandc0",
"clk_nandc1", "clk_gpu",
"pclk_pd_pmu", "g_clk_pvtm_core",
"g_clk_pvtm_gpu", "g_hdmi_cec_clk",
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@0178 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0178 0x4>;
clocks =
<&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&dummy>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_hp_matrix", "g_pp_axi_matrix",
"g_ap_axi_matrix", "g_aclk_dmac2",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
"g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@017c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x017c 0x4>;
clocks =
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_pclk_i2c5", "g_pclk_saradc",
"g_pclk_tsadc", "g_pclk_sim",
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
"g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@0180 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0180 0x4>;
clocks =
<&aclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hsadc_0_tsp>,
<&hsadc_1_tsp>, <&io_27m_in>,
<&aclk_peri>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_gmac", "g_pclk_gmac",
"g_hclk_gps", "g_hclk_sdmmc",
"g_hclk_sdio0", "g_hclk_sdio1",
"g_hclk_emmc", "g_hclk_hsadc",
"g_hclk_tsp", "g_hsadc_0_tsp",
"g_hsadc_1_tsp", "g_clk_27m_tsp",
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@0184 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0184 0x4>;
clocks =
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates10: gate-clk@0188 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0188 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&pclk_bus>, <&pclk_bus>;
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
"g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
"g_hclk_i2s", "g_hclk_rom",
"g_hclk_spdif", "g_h_spdif_8ch",
"g_aclk_dmac1", "g_aclk_strc_sys",
"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
//rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
#clock-cells = <1>;
};
clk_gates11: gate-clk@018c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x018c 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&aclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
"g_p_efuse_1024", "g_pclk_tzpc",
"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
"g_aclk_crypto", "g_hclk_crypto",
"g_aclk_ccp", "g_pclk_uart2",
"g_p_efuse_256", "g_pclk_rkpwm",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
clk_gates12: gate-clk@0190 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0190 0x4>;
clocks =
<&clk_core0>, <&clk_core1>,
<&clk_core2>, <&clk_core3>,
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"clk_core0", "clk_core1",
"clk_core2", "clk_core3",
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
"pclk_dbg_src", "g_dbg_core_clk",
"g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
clk_gates13: gate-clk@0194 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
<&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&aclk_bus_src>, <&xin12m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&aclk_hevc>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
"clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
"g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates14: gate-clk@0198 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0198 0x4>;
clocks =
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "g_pclk_gpio1",
"g_pclk_gpio2", "g_pclk_gpio3",
"g_pclk_gpio4", "g_pclk_gpio5",
"g_pclk_gpio6", "g_pclk_gpio7",
"g_pclk_gpio8", "reserved",
"reserved", "g_pclk_grf",
"g_p_alive_niu", "reserved",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
clk_gates15: gate-clk@019c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
<&clk_gates15 11>, <&hclk_vio>,
<&dummy>, <&clk_gates15 11>,
<&hclk_vio>, <&clk_gates15 12>,
<&hclk_vio>, <&dummy>,
<&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
<&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
"reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
"g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
"reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates16: gate-clk@01a0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
<&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclkin_cif", "g_hclk_isp",
"g_aclk_isp", "g_pclkin_isp",
"g_p_mipi_dsi0", "g_p_mipi_dsi1",
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
"reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates17: gate-clk@01a4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a4 0x4>;
clocks =
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclk_pmu", "g_pclk_intmem1",
"g_pclk_pmu_niu", "g_pclk_sgrf",
"g_pclk_gpio0", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
clk_gates18: gate-clk@01a8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a8 0x4>;
clocks =
<&clk_gpu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", /*"g_aclk_gpu",*/ "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
};
};
};
};