关键词：rk3036-pinctrl.dtsi ,linux_3.10,rockchip,dts
dts — rk3036-pinctrl.dtsi
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pinctrl/rockchip-rk3036.h>
/ {
pinctrl: pinctrl@20008000 {
compatible = "rockchip,rk3036-pinctrl";
reg = <0x20008000 0xA8>,
<0x200080A8 0x30>,
<0x20008118 0x18>,
<0x20008100 0x04>;
reg-names = "base", "mux", "pull", "drv";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio15: gpio15@20086000 {
compatible = "rockchip,gpio-bank";
reg = <0x20086000 0x100>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;//127 = 160-32-1
clocks = <&clk_gates8 12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
};
pcfg_pull_down: pcfg_pull_down {
bias-pull-down;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
gpio0_uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <UART0_SIN>,
<UART0_SOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart0_cts: uart0-cts {
rockchip,pins = <UART0_CTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart0_rts: uart0-rts {
rockchip,pins = <UART0_RTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart0_rts_gpio: uart0-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART0_RTSN)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <UART1_SIN>,
<UART1_SOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <UART2_SIN>,
<UART2_SOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
/* no rts / cts for uart2 */
};
gpio0_i2c0 {
i2c0_sda:i2c0-sda {
rockchip,pins = <I2C0_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c0_scl:i2c0-scl {
rockchip,pins = <I2C0_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c0_gpio: i2c0-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C0_SDA)>, <FUNC_TO_GPIO(I2C0_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_i2c1 {
i2c1_sda:i2c1-sda {
rockchip,pins = <I2C1_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c1_scl:i2c1-scl {
rockchip,pins = <I2C1_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c1_gpio: i2c1-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C1_SDA)>, <FUNC_TO_GPIO(I2C1_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio2_i2c2 {
i2c2_sda:i2c2-sda {
rockchip,pins = <I2C2_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c2_scl:i2c2-scl {
rockchip,pins = <I2C2_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c2_gpio: i2c2-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C2_SDA)>, <FUNC_TO_GPIO(I2C2_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_spi0 {
spi0_txd:spi0-txd {
rockchip,pins = <SPI0_TXD>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_rxd:spi0-rxd {
rockchip,pins = <SPI0_RXD>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_clk:spi0-clk {
rockchip,pins = <SPI0_CLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs0:spi0-cs0 {
rockchip,pins = <SPI0_CS0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs1:spi0-cs1 {
rockchip,pins = <SPI0_CS1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_hdmi {
hdmi_cec:hdmi-cec {
rockchip,pins = <HDMI_CEC>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_sda:hdmi-sda {
rockchip,pins = <HDMI_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_scl:hdmi-scl {
rockchip,pins = <HDMI_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_hpd:hdmi-hpd {
rockchip,pins = <HDMI_HPD>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_gpio: hdmi-gpio {
rockchip,pins = <FUNC_TO_GPIO(HDMI_CEC)>, <FUNC_TO_GPIO(HDMI_SDA)>, <FUNC_TO_GPIO(HDMI_SCL)>, <FUNC_TO_GPIO(HDMI_HPD)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio1_i2s0 {
i2s0_mclk:i2s0-mclk {
rockchip,pins = <I2S0_MCLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sclk:i2s0-sclk {
rockchip,pins = <I2S0_SCLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrckrx:i2s0-lrckrx {
rockchip,pins = <I2S0_LRCKRX>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrcktx:i2s0-lrcktx {
rockchip,pins = <I2S0_LRCKTX>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdo:i2s0-sdo {
rockchip,pins = <I2S0_SDO>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdi:i2s0-sdi {
rockchip,pins = <I2S0_SDI>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_gpio: i2s0-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2S0_MCLK)>,
<FUNC_TO_GPIO(I2S0_SCLK)>,
<FUNC_TO_GPIO(I2S0_LRCKRX)>,
<FUNC_TO_GPIO(I2S0_LRCKTX)>,
<FUNC_TO_GPIO(I2S0_SDO)>,
<FUNC_TO_GPIO(I2S0_SDI)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_spdif {
spdif_tx: spdif-tx {
rockchip,pins = <SPDIF_TX>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_emmc0 {
emmc0_clk: emmc0-clk {
rockchip,pins = <EMMC_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
emmc0_cmd: emmc0-cmd {
rockchip,pins = <EMMC_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
};
emmc0_bus1: emmc0-bus-width1 {
rockchip,pins = <EMMC_D0>;
rockchip,pull = <VALUE_PULL_UP>;
};
emmc0_bus4: emmc0-bus-width4 {
rockchip,pins = <EMMC_D0>,
<EMMC_D1>,
<EMMC_D2 >,
<EMMC_D3>;
rockchip,pull = <VALUE_PULL_UP>;
};
};
gpio1_sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
rockchip,pins = <MMC0_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins = <MMC0_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_dectn: sdmmc0-dectn{
rockchip,pins = <MMC0_DETN>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_bus1: sdmmc0-bus-width1 {
rockchip,pins = <MMC0_D0>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_bus4: sdmmc0-bus-width4 {
rockchip,pins = <MMC0_D0>,
<MMC0_D1>,
<MMC0_D2>,
<MMC0_D3>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_gpio: sdmmc0_gpio{
rockchip,pins =
<GPIO1_B7>, //CMD
<GPIO1_C0>, //CLK
<GPIO1_C1>, //DET
<GPIO1_C2>, //D0
<GPIO1_C3>, //D1
<GPIO1_C4>, //D2
<GPIO1_C5>; //D3
rockchip,pull = <VALUE_PULL_UP>;
};
};
gpio1_nandc {
nandc_ale:nandc-ale {
rockchip,pins = <NAND_ALE>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_cle:nandc-cle {
rockchip,pins = <NAND_CLE>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_wrn:nandc-wrn {
rockchip,pins = <NAND_WRN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_rdn:nandc-rdn {
rockchip,pins = <NAND_RDN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_rdy:nandc-rdy {
rockchip,pins = <NAND_RDY>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_cs0:nandc-cs0 {
rockchip,pins = <NAND_CS0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_data: nandc-data {
rockchip,pins = <NAND_D0>,
<NAND_D1>,
<NAND_D2>,
<NAND_D3>,
<NAND_D4>,
<NAND_D5>,
<NAND_D6>,
<NAND_D7>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_sdio0 {
sdio0_clk: sdio0_clk {
rockchip,pins = <MMC1_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
sdio0_cmd: sdio0_cmd {
rockchip,pins = <MMC1_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdio0_bus1: sdio0-bus-width1 {
rockchip,pins = <MMC1_D0>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdio0_bus4: sdio0-bus-width4 {
rockchip,pins = <MMC1_D0>,
<MMC1_D1>,
<MMC1_D2>,
<MMC1_D3>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdio0_gpio: sdio0-all-gpio{
rockchip,pins =
<GPIO0_B1>, //CLK
<GPIO0_B0>, //CMD
<GPIO0_B3>, //DO
<GPIO0_B4>, //D1
<GPIO0_B5>, //D2
<GPIO0_B6>; //D3
rockchip,pull = <VALUE_PULL_UP>;
};
};
gpio0_pwm{
pwm0_pin:pwm0 {
rockchip,pins = <PWM0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm1_pin:pwm1 {
rockchip,pins = <PWM1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm2_pin:pwm2 {
rockchip,pins = <PWM2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm3_pin:pwm3 {
rockchip,pins = <PWM3(IR)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio2_gmac {
mac_clk: mac-clk {
rockchip,pins = <MAC_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
mac_txpins: mac-txpins {
rockchip,pins = <MAC_TXD0>, <MAC_TXD1>, <MAC_TXEN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
mac_rxpins: mac-rxpins {
rockchip,pins = <MAC_RXD0>, <MAC_RXD1>,<MAC_RXER>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
mac_crs: mac-crs {
rockchip,pins = <MAC_CRS>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
mac_mdpins: mac-mdpins {
rockchip,pins = <MAC_MDIO>, <MAC_MDC>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
//to add
};
};
>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_33: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_33";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc18_lcd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_lan: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_lan";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_wl: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
rk808_ldo10_reg: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "rk_ldo10";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tc358749x: tc358749x@0f {
compatible = "toshiba,tc358749x";
reg = <0x0f>;
power-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
stanby-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio8 8 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio8 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hdmiin_gpios>;
status = "okay";
};
};
&i2c2 {
status = "okay";
es8323: es8323@10 {
status = "okay";
compatible = "everest,es8323";
reg = <0x10>;
spk-con-gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
hp-det-gpio = <&gpio7 15 GPIO_ACTIVE_LOW>;
clock-names = "mclk";
clocks = <&cru SCLK_I2S0_OUT>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
#sound-dai-cells = <0>;
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
gsl3680: gsl3680@40 {
status = "okay";
compatible = "gslX680";
reg = <0x40>;
screen_max_x = <1536>;
screen_max_y = <2048>;
flip-x = <1>;
flip-y = <1>;
touch-gpio = <&gpio7 13 IRQ_TYPE_EDGE_RISING>;
};
};
&i2s {
#sound-dai-cells = <0>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&isp {
/delete-property/ rockchip,gpios;
status = "okay";
};
&isp_mmu {
status = "okay";
};
&vpu_service {
status = "okay";
};
&usb_host0_ehci {
rockchip-relinquish-port;
status = "okay";
};
&vopb {
status = "okay";
};
&vopl {
status = "okay";
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dfi {
status = "okay";
};
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0x0 0xff600000 0x0 0x4000>;
};
&dmc {
center-supply = <&vdd_gpu>;
status = "okay";
};
&efuse {
compatible = "rockchip,rk3288-secure-efuse";
};
&rga {
compatible = "rockchip,rga2";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
};
&rockchip_suspend {
status = "okay";
};
&usb_otg {
compatible = "rockchip,rk3288_usb20_otg";
clocks = <&usbphy0>, <&cru HCLK_OTG0>;
clock-names = "clk_usbphy0", "hclk_usb0";
resets = <&cru SRST_USBOTG_AHB>,
<&cru SRST_USBOTG_PHY>,
<&cru SRST_USBOTG_CON>;
reset-names = "otg_ahb", "otg_phy", "otg_controller";
/*0 - Normal, 1 - Force Host, 2 - Force Device*/
rockchip,usb-mode = <0>;
status = "okay";
};
&pwm0 {
status = "okay";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
compatible = "rockchip,remotectl-pwm";
remote_pwm_id = <0>;
handle_cpu_id = <0>;
ir_key1{
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xeb KEY_POWER>,
<0xec KEY_MENU>,
<0xfe KEY_BACK>,
<0xb7 KEY_HOME>,
<0xa3 KEY_WWW>,
<0xf4 KEY_VOLUMEUP>,
<0xa7 KEY_VOLUMEDOWN>,
<0xf8 KEY_REPLY>,
<0xfc KEY_UP>,
<0xfd KEY_DOWN>,
<0xf1 KEY_LEFT>,
<0xe5 KEY_RIGHT>;
};
};
&tsadc {
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
&pinctrl {
/* sata:gpio0 c1 */
init-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
pcfg_output_high: pcfg-output-high {
output-high;
};
pcfg_output_low: pcfg-output-low {
output-low;
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
eth_phy {
eth_phy_pwr: eth-phy-pwr {
rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_cs: lcd-cs {
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
};
lcd_en: lcd-en {
rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
act8846 {
pmic_vsel: pmic-vsel {
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
};
pwr_hold: pwr-hold {
rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
};
};
backlight {
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hdmiin {
hdmiin_gpios: hdmiin_gpios {
rockchip,pins =
<7 5 RK_FUNC_GPIO &pcfg_pull_none>,
<7 21 RK_FUNC_GPIO &pcfg_pull_none>,
<8 8 RK_FUNC_GPIO &pcfg_pull_none>,
<8 9 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
or-state-uv = <1800000>;
};
};
/* SDMMC IO, 3.3V*/
rk808_ldo5_reg: regulator@8 {
regulator-name= "rk_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
/* CAMERA, 1.8V box modify*/
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1000000>;
};
};
/* RK3288 USB PHY, SAR-ADC, WIFI IO, 1.8V */
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
/* DTV, 3.3V box modify*/
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk808_ldo9_reg: regulator@12 {
regulator-name= "rk_ldo9";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
rk808_ldo10_reg: regulator@13 {
regulator-name= "rk_ldo10";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
};
};
};
};
&lcdc_vdd_domain {
regulator-name = "vcc30_lcd";
};
&dpio_vdd_domain{
regulator-name = "vcc18_cif";
};
&flash0_vdd_domain{
regulator-name = "vcc_flash";
};
&flash1_vdd_domain{
regulator-name = "vcc_flash";
};
&apio3_vdd_domain{
regulator-name = "vccio_wl";
};
&apio5_vdd_domain{
regulator-name = "vccio";
};
&apio4_vdd_domain{
regulator-name = "vccio";
};
&apio1_vdd_domain{
regulator-name = "vccio";
};
&apio2_vdd_domain{
regulator-name = "vccio";
};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
/*
* Due to not have the software of PWM for remotectrl.
* We can _*HACK*_ do that as the following.
*/
&pwm0 {
compatible = "rockchip,remotectl-pwm";
remote_pwm_id = <0>;
handle_cpu_id = <1>;
status = "okay";
ir_key1{
rockchip,usercode = <0x4040>;
rockchip,key_table =
<0xf2 KEY_REPLY>,
<0xba KEY_BACK>,
<0xf4 KEY_UP>,
<0xf1 KEY_DOWN>,
<0xef KEY_LEFT>,
<0xee KEY_RIGHT>,
<0xbd KEY_HOME>,
<0xea KEY_VOLUMEUP>,
<0xe3 KEY_VOLUMEDOWN>,
<0xe2 KEY_SEARCH>,
<0xb2 KEY_POWER>,
<0xbc KEY_MUTE>,
<0xec KEY_MENU>,
<0xbf 0x190>,
<0xe0 0x191>,
<0xe1 0x192>,
<0xe9 183>,
<0xe6 248>,
<0xe8 185>,
<0xe7 186>,
<0xf0 388>,
<0xbe 0x175>;
};
ir_key2{
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_VOLUMEDOWN>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xbe KEY_SEARCH>;
};
ir_key3{
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
};
#clock-cells = <0>;
};
};
clk_sel_con12: sel-con@0090 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0090 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_sdio0_div: clk_sdio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&clk_sdio0>;
clock-output-names = "clk_sdio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio0: clk_sdio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio0";
#clock-cells = <0>;
};
clk_emmc_div: clk_emmc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_emmc>;
clock-output-names = "clk_emmc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_emmc: clk_emmc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_emmc";
#clock-cells = <0>;
};
};
clk_sel_con13: sel-con@0094 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0094 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart0_pll_div: clk_uart0_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart0_pll>;
clock-output-names = "clk_uart0_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[7]: reserved */
clk_uart0: uart0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart0";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[10]: reserved */
usbphy_480m: usbphy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <11 2>;
clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>;
clock-output-names = "usbphy_480m";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_USB480M>;
#clock-init-cells = <1>;
};
clk_uart0_pll: clk_uart0_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_uart0_pll";
#clock-cells = <0>;
};
uart_pll_mux: uart_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "uart_pll_mux";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con14: sel-con@0098 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0098 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart1_div: clk_uart1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart1_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart1: uart1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart1";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con15: sel-con@009c {
compatible = "rockchip,rk3188-selcon";
reg = <0x009c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart2_div: clk_uart2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart2_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart2: uart2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart2";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con16: sel-con@00a0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart3_div: clk_uart3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart3_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart3: uart3_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart3";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con17: sel-con@00a4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart0_frac: uart0_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart0_pll>;
clock-output-names = "uart0_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con18: sel-con@00a8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart1_frac: uart1_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart1_div>;
clock-output-names = "uart1_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con19: sel-con@00ac {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ac 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart2_frac: uart2_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart2_div>;
clock-output-names = "uart2_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con20: sel-con@00b0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart3_frac: uart3_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart3_div>;
clock-output-names = "uart3_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con21: sel-con@00b4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_mac_pll: clk_mac_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_mac_pll";
#clock-cells = <0>;
};
/* reg[3:2]: reserved */
clk_mac: clk_mac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_mac_pll>, <&gmac_clkin>;
clock-output-names = "clk_mac";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MAC_REF>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
clk_mac_pll_div: clk_mac_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_mac_pll>;
clock-output-names = "clk_mac_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[15:13]: reserved */
};
clk_sel_con22: sel-con@00b8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hsadc_pll: clk_hsadc_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_hsadc_pll";
#clock-cells = <0>;
};
/*
wifi_pll_mux: wifi_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <1 1>;
clocks = <&>, <&>;
clock-output-names = "wifi_pll_mux";
#clock-cells = <0>;
};
*/
/* reg[3:2]: reserved */
clk_hsadc_out: clk_hsadc_out {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
clock-output-names = "clk_hsadc_out";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_HSADC>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[6:5]: reserved */
clk_hsadc: clk_hsadc {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
clock-output-names = "clk_hsadc";
#clock-cells = <0>;
};
clk_hsadc_pll_div: clk_hsadc_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&clk_hsadc_pll>;
clock-output-names = "clk_hsadc_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
};
/*
clk_sel_con23: sel-con@00bc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00bc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
wifi_frac: wifi_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&>;
clock-output-names = "wifi_frac";
/ numerator denominator /
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<>;
#clock-cells = <0>;
};
};
*/
clk_sel_con24: sel-con@00c0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
/* reg[7:0]: reserved */
clk_saradc: clk_saradc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&xin24m>;
clock-output-names = "clk_saradc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
};
clk_sel_con25: sel-con@00c4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi0_div: clk_spi0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi0>;
clock-output-names = "clk_spi0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi0: clk_spi0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi0";
#clock-cells = <0>;
};
clk_spi1_div: clk_spi1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 7>;
clocks = <&clk_spi1>;
clock-output-names = "clk_spi1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi1: clk_spi1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi1";
#clock-cells = <0>;
};
};
clk_sel_con26: sel-con@00c8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ddr_div: ddr_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 2>;
clocks = <&clk_ddr>;
clock-output-names = "clk_ddr";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
<0x0 1
0x1 2
0x3 4>;
#clock-cells = <0>;
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
};
clk_ddr: ddr_clk_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_dpll>, <&clk_gpll>;
clock-output-names = "clk_ddr";
#clock-cells = <0>;
};
/* reg[5:3]: reserved */
clk_crypto: crypto_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <6 2>;
clocks = <&aclk_bus>;
clock-output-names = "clk_crypto";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_cif_pll: clk_cif_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_cif_pll";
#clock-cells = <0>;
};
clk_cif_out_div: clk_cif_out_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_cif_out>;
clock-output-names = "clk_cif_out";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14]: reserved */
clk_cif_out: clk_cif_out_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_cif_pll>, <&xin24m>;
clock-output-names = "clk_cif_out";
#clock-cells = <0>;
};
};
clk_sel_con27: sel-con@00cc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00cc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
dclk_lcdc0: dclk_lcdc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc0";
#clock-cells = <0>;
};
/* reg[7:2]: reserved */
dclk_lcdc0_div: dclk_lcdc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc0>;
clock-output-names = "dclk_lcdc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC0>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con28: sel-con@00d0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_edp_div: clk_edp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&clk_edp>;
clock-output-names = "clk_edp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_edp: clk_edp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_edp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
hclk_vio: hclk_vio_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gates15 11>;
clock-output-names = "hclk_vio";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[14:13]: reserved */
clk_edp_24m: edp_24m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&edp_24m_clkin>, <&xin24m>;
clock-output-names = "clk_edp_24m";
#clock-cells = <0>;
};
};
clk_sel_con29: sel-con@00d4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ehci1phy_480m: ehci1phy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "ehci1phy_480m";
#clock-cells = <0>;
};
ehci1phy_12m: ehci1phy_12m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
clock-output-names = "ehci1phy_12m";
#clock-cells = <0>;
};
clkin_isp: clkin_isp {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <3 1>;
clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
clock-output-names = "clkin_isp";
#clock-cells = <0>;
};
clkin_cif: clkin_cif {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
clock-output-names = "clkin_cif";
#clock-cells = <0>;
};
/* reg[5]: reserved */
dclk_lcdc1: dclk_lcdc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc1";
#clock-cells = <0>;
};
dclk_lcdc1_div: dclk_lcdc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc1>;
clock-output-names = "dclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC1>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con30: sel-con@00d8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_rga_div: aclk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_rga>;
clock-output-names = "aclk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_rga_div: clk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_rga>;
clock-output-names = "clk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con31: sel-con@00dc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00dc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_vio0_div: aclk_vio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_vio0>;
clock-output-names = "aclk_vio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[5]: reserved */
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_vio1_div: aclk_vio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_vio1>;
clock-output-names = "aclk_vio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00e0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_vepu_div: clk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_vdpu_div: clk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con33: sel-con@00e4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
pclk_pd_pmu: pclk_pd_pmu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_pmu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
pclk_pd_alive: pclk_pd_alive {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_alive";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:13]: reserved */
};
clk_sel_con34: sel-con@00e8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_sdio1_div: clk_sdio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_sdio1>;
clock-output-names = "clk_sdio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
};
clk_sel_con35: sel-con@00ec {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ec 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_tsp_div: clk_tsp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_tsp>;
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_tspout_div: clk_tspout_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_tspout>;
clock-output-names = "clk_tspout";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con36: sel-con@00f0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_core0: clk_core0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
clk_core1: clk_core1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[7]: reserved */
clk_core2: clk_core2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[11]: reserved */
clk_core3: clk_core3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core3";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15]: reserved */
};
clk_sel_con37: sel-con@00f4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_l2ram: clk_l2ram_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_l2ram";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
atclk_core: atclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 5>;
clocks = <&clk_core>;
clock-output-names = "atclk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
pclk_dbg_src: pclk_core_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg_src";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15:14]: reserved */
};
clk_sel_con38: sel-con@00f8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_nandc0_div: clk_nandc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_nandc0>;
clock-output-names = "clk_nandc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[6:5]: reserved */
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1_div: clk_nandc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_nandc1>;
clock-output-names = "clk_nandc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14:13]: reserved */
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
};
clk_sel_con39: sel-con@00fc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00fc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi2_div: clk_spi2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi2>;
clock-output-names = "clk_spi2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
aclk_hevc_div: aclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_hevc>;
clock-output-names = "aclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con40: sel-con@0100 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0100 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_div: spdif_8ch_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spdif_pll>;
clock-output-names = "spdif_8ch_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif_8ch: spdif_8ch_clk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
clock-output-names = "clk_spdif_8ch";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
hclk_hevc: hclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_hevc>;
clock-output-names = "hclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:14]: reserved */
};
clk_sel_con41: sel-con@0104 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0104 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_frac: spdif_8ch_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&spdif_8ch_div>;
clock-output-names = "spdif_8ch_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con42: sel-con@0108 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0108 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hevc_cabac_div: clk_hevc_cabac_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_hevc_cabac>;
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_hevc_core_div: clk_hevc_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_hevc_core>;
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@0160 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0160 0x4>;
clocks =
<&dummy>, <&clk_apll>,
<&clk_gpll>, <&aclk_bus>,
<&hclk_bus>, <&pclk_bus>,
<&dummy>, <&aclk_bus>,
<&clk_dpll>, <&clk_gpll>,
<&clk_gpll>, <&clk_cpll>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /* do not use bit1 = "core_apll" */
"clk_arm_gpll", "g_aclk_bus",
"hclk_bus", "pclk_bus",
"reserved", "aclk_bus_2pmu",
"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@0164 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0164 0x4>;
clocks =
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&clk_uart0_pll>, <&uart0_frac>,
<&clk_uart1_div>, <&uart1_frac>,
<&clk_uart2_div>, <&uart2_frac>,
<&clk_uart3_div>, <&uart3_frac>;
clock-output-names =
"clk_timer0", "clk_timer1",
"clk_timer2", "clk_timer3",
"clk_timer4", "clk_timer5",
"reserved", "reserved",
"clk_uart0_pll", "uart0_frac",
"clk_uart1_div", "uart1_frac",
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@0168 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0168 0x4>;
clocks =
<&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&dummy>, <&clk_mac_pll>,
<&clk_hsadc_pll>, <&clk_tsadc>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_spi2>,
<&clk_uart4_div>, <&uart4_frac>,
<&dummy>, <&dummy>;
clock-output-names =
"aclk_peri", "reserved", /*"g_aclk_periph",*/
"hclk_peri", "pclk_peri",
"reserved", "clk_mac_pll",
"clk_hsadc_pll", "clk_tsadc",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_spi2",
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@016c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x016c 0x4>;
clocks =
<&aclk_vio0>, <&dclk_lcdc0>,
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
<&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
<&clk_edp_24m>, <&clk_edp>,
<&clk_isp>, <&clk_isp_jpe>;
clock-output-names =
"aclk_vio0", "dclk_lcdc0",
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
"ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"reserved", "clk_vdpu",
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@0170 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
<&clk_i2s_out>, <&clk_i2s_pll>,
<&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&spdif_8ch_frac>, <&clk_spdif_8ch>,
<&clk_tsp>, <&clk_tspout>,
<&clk_ddr>, <&clk_ddr>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
"clk_i2s_out", "clk_i2s_pll",
"i2s_frac", "clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"spdif_8ch_frac", "clk_spdif_8ch",
"clk_tsp", "clk_tspout",
/* Not use these ddr gates */
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@0174 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0174 0x4>;
clocks =
<&clk_mac>, <&clk_mac>,
<&clk_mac>, <&clk_mac>,
<&clk_crypto>, <&clk_nandc0>,
<&clk_nandc1>, <&clk_gpu>,
<&pclk_pd_pmu>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&xin24m>, <&xin24m>,
<&usbphy_480m>, <&xin24m>;
clock-output-names =
"g_clk_mac_rx", "g_clk_mac_tx",
"g_clk_mac_ref", "g_mac_refout",
"clk_crypto", "clk_nandc0",
"clk_nandc1", "clk_gpu",
"pclk_pd_pmu", "g_clk_pvtm_core",
"g_clk_pvtm_gpu", "g_hdmi_cec_clk",
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@0178 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0178 0x4>;
clocks =
<&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&dummy>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_hp_matrix", "g_pp_axi_matrix",
"g_ap_axi_matrix", "g_aclk_dmac2",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
"g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@017c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x017c 0x4>;
clocks =
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_pclk_i2c5", "g_pclk_saradc",
"g_pclk_tsadc", "g_pclk_sim",
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
"g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@0180 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0180 0x4>;
clocks =
<&aclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hsadc_0_tsp>,
<&hsadc_1_tsp>, <&io_27m_in>,
<&aclk_peri>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_gmac", "g_pclk_gmac",
"g_hclk_gps", "g_hclk_sdmmc",
"g_hclk_sdio0", "g_hclk_sdio1",
"g_hclk_emmc", "g_hclk_hsadc",
"g_hclk_tsp", "g_hsadc_0_tsp",
"g_hsadc_1_tsp", "g_clk_27m_tsp",
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@0184 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0184 0x4>;
clocks =
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates10: gate-clk@0188 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0188 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&pclk_bus>, <&pclk_bus>;
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
"g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
"g_hclk_i2s", "g_hclk_rom",
"g_hclk_spdif", "g_h_spdif_8ch",
"g_aclk_dmac1", "g_aclk_strc_sys",
"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
//rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
#clock-cells = <1>;
};
clk_gates11: gate-clk@018c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x018c 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&aclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
"g_p_efuse_1024", "g_pclk_tzpc",
"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
"g_aclk_crypto", "g_hclk_crypto",
"g_aclk_ccp", "g_pclk_uart2",
"g_p_efuse_256", "g_pclk_rkpwm",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
clk_gates12: gate-clk@0190 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0190 0x4>;
clocks =
<&clk_core0>, <&clk_core1>,
<&clk_core2>, <&clk_core3>,
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"clk_core0", "clk_core1",
"clk_core2", "clk_core3",
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
"pclk_dbg_src", "g_dbg_core_clk",
"g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
clk_gates13: gate-clk@0194 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
<&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&aclk_bus_src>, <&xin12m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&aclk_hevc>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
"clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
"g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates14: gate-clk@0198 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0198 0x4>;
clocks =
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "g_pclk_gpio1",
"g_pclk_gpio2", "g_pclk_gpio3",
"g_pclk_gpio4", "g_pclk_gpio5",
"g_pclk_gpio6", "g_pclk_gpio7",
"g_pclk_gpio8", "reserved",
"reserved", "g_pclk_grf",
"g_p_alive_niu", "reserved",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
clk_gates15: gate-clk@019c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
<&clk_gates15 11>, <&hclk_vio>,
<&dummy>, <&clk_gates15 11>,
<&hclk_vio>, <&clk_gates15 12>,
<&hclk_vio>, <&dummy>,
<&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
<&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
"reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
"g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
"reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates16: gate-clk@01a0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
<&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclkin_cif", "g_hclk_isp",
"g_aclk_isp", "g_pclkin_isp",
"g_p_mipi_dsi0", "g_p_mipi_dsi1",
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
"reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates17: gate-clk@01a4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a4 0x4>;
clocks =
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclk_pmu", "g_pclk_intmem1",
"g_pclk_pmu_niu", "g_pclk_sgrf",
"g_pclk_gpio0", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
clk_gates18: gate-clk@01a8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a8 0x4>;
clocks =
<&clk_gpu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", /*"g_aclk_gpu",*/ "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
};
};
};
};